All Programmable Planet
Today All Programmable Planet’s newsletter appeared in my inbox, with a great post by Max Maxfield on the Xilinx family of 3D FPGAs. Beyond the detailed descriptions of Xilinx’ products, and explanation between the difference between 3D FPGA and 3D Heterogeneous FPGA, I especially like Max’s musings on page two, about the realm of possibilities that could be achieved with 3D ICS in analog, programmable SoC’s, optical, and more. After putting forth his sky’s-the-limit wish list, he asks for reader’s dream device. So be sure to add to the list!
I was hoping to find something about the company’s switch in terminology from 2.5D to 3D (especially after yesterday’s review of Vincent Tong’s Keynote at the 3D IC Technology Forum at SEMICON Taiwan), but there was none. I even posted a question to Max about it, but he’s in the dark as much as I am. However, unlike me, he says he preferred the 2.5D terminology. I’d love to get to the bottom of this. Any 3D InCites members from Xilinx care to provide the answer?
3D simulation to enable 3D design of 3D transistors and even TSVs for 3DICS? That’s a lot of 3D, but why not? Blogger John Blyler shares his experience in words and video playing with Dassault Systemes’s virtual-reality development and deployment system, 3DVIA. Blyler notes that “such a system might seem like overkill for the world of chip design (ya think?) But as Blyler points out that for FinFETS, TSVs and even MEMS, virtual realitysimulations could be used to visualize the effects of evolving transistor structures, or to enhance the accuracy of thermal flows around stacked die.
On Oct 9 in EETimes, Peter Clarke reports that TSMC has prepared reference design flows to support its chip on wafer on substrate (CoWoS) process within its Open Innovation Platform (IOP). This multi-die on interposer technology has been validated with silicon runs, and TSMC is ready to accept design starts, notes Clarke. So designers, roll up your sleeves and get busy! TSMC is ready for you.
Solid State Technology
While this news item isn’t specifically 3D IC related, Pete Singer’s report on the formation of Silicon Europe is pretty important to the 3D IC world, since European research centers such as imec, Fraunhofer IZM-ASSID, and CEA-Leti have all been instrumental in bringing 3DICs to the forefront of technology. Silicon Europe brings together the four European micro- and nanoelectronics regions comprising Silicon Saxony (Dresden/Germany), DSP Valley (Belgium), Minalogic (Grenoble/France) and Point One (Eindhoven/Netherlands) to form a cluster alliance that will cooperate in research, development and business. Read on for details.
Earlier this week and just in time for SEMICON Europa, SPTS and Fraunhofer announced a JDP to research sub-175ºC dielectric films in through silicon vias (TSV) for 3D-IC packaging. The program will use 300mm APM plasma enhanced chemical vapor deposition (PECVD) modules installed on a Versalis® platform alongside SPTS etch chambers in the All Silicon System Integration Dresden (ASSID) center in Dresden, Germany. I know that SPTS has been working with ASSID for quite some time, because I’ve seen the tools there myself and have the video to prove it. But this is a new project. Here’s the full press release.
I can’t believe this one almost slipped my radar. I just found this press release from today, by way of ChipEstimate’s website. Synopsys announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC’s CoWoS™ (Chip on Wafer on Substrate) Reference Flow. According to the company, the solution comes in the form of “enhanced versions of its Galaxy Implementation Platform tools for physical implementation, parasitic extraction, physical verification and timing analysis.” The two companies have reportedly been collaborating to develop “a smooth transition from 2D IC design to multi-die stack design flows. Synopsys has long held its position that its 2D tools, with adaptations, are sufficent for current 3D IC design needs. Here’s the full press release.