Guest contributor, Herb Reiter, reports from the Sept 13 meeting of the GSA’s 3D/TSV EDA Interest Group, where 55 attendees, both physical and virtual, heard 3D progress reports from academia, manufacturing, and market research entities. For those of you who missed it, Herb provided the following minutes of the meeting:

Herb Reiter opened with encouraging news about continued IC revenue growth that’s expected for the next several years and increasing numbers of design starts since 1Q2009. He also shared recent analysis from Gartner DQ that not only demonstrates that consumer products are a very large part of the semiconductor market, but also emphasizes that tablet PCs,smartphones and mobile PCs will be the most important high-growth and high-revenue devices for the next few years.

All three categories are both power- and space constraint and demand high-performance computing power. They represent ideal opportunities for the power- and space-saving 3D/TSV technology.

Yuan Xie from Penn State University called in from Asia (1am his time) to explain the cost benefits and trade-offs of 3D/TSV designs and talk about several of his 3D projects from Penn State. Based on his extensive work with leading edge IC vendors, he shared what these teams learned about the cost savings possible for medium and large logic designs if partitioned into several higher yielding smaller chips, with fewer metal layers.

Yuan also talked about the results of an Intel study with heterogeneous process technologies. Medium size dice suffer a 2X increase in cost, at larger dice sizes Intel found a cost increase of 3X.

Presenting from his office in Grenoble France, Eric Mounier,from Yole Developpment Market Research in France showed how 3D stacking can reduce formfactor, explained the many different TSV manufacturing approaches, then focused on the 3D/TSV cost model Yole has developed, based on inputs from many manufacturers. Several examples demonstrated the flexibility of this cost-model and a real life demo of the cost model concluded his session.

Riko Radojcic from Qualcomm showed the group a proposal for focused and driven 3D standardization Initiative(s). He presented specific ideas where and how R & D teams, industry organizations and standards bodies should work together to build a strong ecosystem in support of high-volume manufacturing of 3D/TSV designs. Radojcic emphasized that our industry doesn’t need to standardize core competencies in specific design- and manufacturing step —where successful vendors typically differentiate themselves, but agreements how individual pieces can fit together in a complete flow.

Additionally, Radojcic mentioned that DRAM vendors are already working within JEDEC on interface standards to facilitate 3D stacking. He praised successful efforts towards standardizing manufacturing steps and pointed out that standards for 3D/TSV design flows are lagging. Existing standards, e.g. IP exact, can be expanded to serve 3D/TSV designers. On a number of slides Radojcic suggested very specific actions and recommended which organizations or industry segments are well suited to address modeling- and design challenges to accelerate 3D design efforts and production ramp-ups. Slide 16 summarizes Qualcomm’s suggestions for program drivers and standards bodies to manage and maintain agreed upon design- and manufacturing methods for 3D/TSV.

Sumit Dasgupta from Si2 first clarified what standards are and what they are not. Then he outlined how the three key 3D design-steps relate to the 3D design environment. Referring to the conclusions of a joint GSA & Si2 event  organized last October, Si2 listed the key goals and actions that Si2 is addressing now. Sumit closed with a list of goals for 2011 to make design tools better interoperable and 3D design flows more productive.

To conclude the meeting, Reiter added  a few more insights and comments. He compared 2D and 3D strengths and weaknesses in a color table. Using slides from a recent GlobalFoundries & Cadence 3D webinar, he outlined the currently widely discussed “2 .5D or interposer” solution versus 3D/TSV stacks. A recently announced partnership between INTEL and ALTERA also focuses on a 2 1/2 D solution comprised on an ATOM processor and an FPGA.

Using a slide from the recent HOTCHIPS conference Herb showed that Microsoft and IBM chose – for cost-reasons – to implement the new XBox 360 chip as a 2 1/2 D solution. They separated the 10 MB eDRAM from the CPU & GPU SoC and placed them side-by-side.

Like the previous two speakers, Reiter emphasized that successful and cost-effective 3D stacking will require industry-wide standards for design and manufacturing of these stacks. Much work remains to be done to agree and implement high-productivity ( = COST EFFECTIVE ) design and manufacturing flows.

Considering the importance of 3D/TSV technology for our industry and the rapidly increasing number of interested parties in the GSA’s 3D efforts and plans, the GSA announced last week a further expansion of the 3D program.

To close the meeting, Reiter asked for input and questions to include in a 3D/TSV questionnaire the GSA will launch in 4Q2010. Suggestions should be emailed to Herb Reiter. ALL slides presented at this meeting (Monday, Sept. 13) are available here for downloadi on the GSA website.

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