I approached the IEDM 2011 conference, in (San Francisco this week) with much trepidation. Surely, most of these presentations would be way over my head from the technical perspective. But I was convinced by Chris Burke and Gary Dagastine of B to B Marketing, that I’d find SOMETHING I understood enough to write about. So I dove in. They were right. I’ve been here for about an hour and already have some interesting nuggets of information for you.
The first plenary speaker, Kinam Kim, of Samsung Electronics, presented a talk entitled “From the Future of SI Technology Perspective: Challenges and Opportunities. I was eager to hear first hand from Samsung what they had to say about this. Are you ready for it? In a nutshell: 3D TSV stacking will be used in NAND Flash; the future of Logic will include a 3D multigate transistor (Samsung has successfully demoed that a sub 5nm MOSFET can be successfully fabricated. SOC 3D stacking for Logic will use TSV technology.
We are all familiar with the advantages of 3D TSVs by now, as well as the challenges. But for the first time, I heard a comparison between PoP stacking and wide I/O TSVs that favored TSVs for package size, power consumption and bandwidth. Despite the still existing challenges of design, process and standardization, there’s no question from Kim’s perspective, “3D Si technology will have to be adopted in technology roadmap.”
Here’s a question I had with regard to NAND flash: for the past few years, it’s been the common understanding that while DRAM is a definite for TSV stacks, it was too costly to be worthwhile for NAND, where wire bond and other alternative methods of interconnect (Vertical Circuits, for example) were sufficient. Yet now Samsung is putting it out there as a growth engine for 3D stacks. Any thoughts or clarifications on this?
The rest of the week, be prepared for lots of information. I’m going to do my best to dole it out as it comes in order to keep from drowning. This afternoon, I’ll be attending session of process technology for advanced 3D that will feature presenters from TSMC, IMEC, Tokyo City University, National Chiao Tung University, IBM TJ Watson Research Center, IMS Chips and CEA Leti. Tomorrow, I’ll be learning about Confluence of Technology and Design- Challenges for Non-Conventional Devices and 3D LSIs. (We’ll see how far I get with that). Then on Wednesday, I’ll be attending the GSA’s EDA 3D Interest Group Meeting in San Jose in the morning, then for the rest of the week, it’s the RTI 3D Systems Integration Conference in Burlingame. At approximately 4:30pm on Friday afternoon, my head will explode. Stay tuned …. F.v.T.