I’ve been waging a campaign this week to bring in new members by contacting all the members of the TSV 3D Packaging Group on LinkedIn individually; the rationale being that anyone participating in LinkedIn groups is really motivated to actively participate in discussions. Well, so far it’s working. In one day we went from 169 members to 193, oh wait, make that 195 (could be more by the time you read this, check the bottom right corner of the home pages screen where the member box is for the most up-to-date count.)
I’ve also been compiling a list of desired topics for more online discussion forums to be held over the next six months, but I could use your help compiling this list. After all, you joined this site to find important information on3D integration developments, so who better to help decide what to cover than the members themselves?
Here’s the plan: we get a list together, and then I go line up the expert panelists, set some dates and we get things rolling. Oh, and if you happen to BE an expert in the area of discussion you’re suggesting, let me know and I’ll sign you up as a panelist.
Here’s what I’ve got so far (the last two courtesy of an email request from a new member):
- 3D MEMS Update
- Alternatives to TSVs
- 3D WLP: the latest on next-generation technologies
- Breakthroughs in 3D image sensor technology
- Interconnect methods for TSV (Chip2Chip,Chip2Wafer,Wafer2Wafer, etc.)
- TSV Reliability Testing: Results/Challenges
So let’s hear it: what would you like to discuss on in the world of 3D integration and packaging? – post your comments/suggestions below, or if you’re too shy, email me at Francoise@3DInCites.com and we’ll add them to the list for consideration. There’s one small hitch – if we run the discussion, you have to promise to ask some questions. Deal? — F.v.T.
Hello All,I am interested in the primary challenges for 3D ICs at circuit level. How about including these topics..1. Challenges in Clock and Power Distribution Networks for 3D ICs (3D Microprocessors)2. Thermal Challenges and circuit level solutions
Francoise and all,
My suggestion is really a complement to the ‘Alternatives To 3D’ and is ‘How far can we go without TSVs?’ I think we all know that widespread use of TSVs for the common man (who needs to interconnect disparate die) is still far away and there is still lots of mileage to be had from existing techniques, especially when one throws in Integrated Passives, silicon interconnects and thinner die.
Krishna and Nick –
Thank you both for these great suggestions. I will add them all to the list and let you know when the discussions have been scheduled. Keep the ideas coming!
Mine would have been along the lines of Nick’s question. Would readers comment on how much they plan to delay TSV adoption because, there are lower risk, less expensive alternatives such as Si Interposer and fan-out WLP. Thanks
Si interposer technology appears to be a good bridge between current 2D and the fully stacked 3D technology. From published literature It appears that the interposers are getting crowded with TSVs, IPDs and may be micro fluidic channels. Since these structures could have different dimensions, can the “gurus” out there comment on the need for process control during interposer production
Rajiv and Arun –
Great questions and comments. Looks like we need to schedule a moderated discussion around Si Interposer technologies. It’s going on the list. In the mean time, I hope we can generate some feedback here!