Attending last week’s TSV Seminar in Tokyo, hosted by Electronic Journal, posed a bit of a challenge as all but one presentation was in Japanese. However, thanks to the detailed diagrams and smatterings of English in the proceedings along with careful note taking by Tegal Corp.’s interpreter Yukumi Hayafune, I was able to summarize the main points of the event.

But first, a word about the different seminar experience from those held in hotels in the US.  The meeting space had a distinct classroom atmosphere, from the white board to the desks. Lunch was a modest affair – cold Bento box and a drink at your desk; networking was a simple business card exchange after the last speaker without the usual corporate sponsored evening reception and/or dinner.  The absence of any table top exhibits was also notable. This was purely an educational event. No bells and whistles.

The morning was devoted to a talk by Dr. Yoshio Mita, associate professor from the Department of Electrical and Electronic Engineering at the University of Tokyo.  Mita-sensei was a lively, animated speaker, drawing frequent laughter from the attendees as he cited his age (young!) at each step in the history of semiconductor processing, plasma etching, and TSVs.

After explaining the well-known benefits of TSV over wire bonding, and the difference between via first, mid and last approaches, Mita-sensei went on to discuss the difference between wet etch and dry etching. Basically, wet processes etch along the crystal plane of the substrate (GaAs or silicon), can be difficult to control, and results in a tapered via. Plasma etch allows for more control and results in straight, even via sidewalls.  Further, when discussing Bosch’s Deep Reactive Ion Etch (DRIE) process, which incorporates a plasma-deposited protective shield of carbon polymer on the sidewalls, Prof. Mita used a bowling with or without bumpers along the alley analogy to what happens with and without the “shielding” polymer. Without it, you get a lot of gutter balls (isotropic etching), while with it you get strikes: better vertical profile control and higher aspect ratio structures.

Prof. Mita went on to compare TSV processes developed by various R&D institutes, the via measurements achieved and target applications.  The example he showed from IMEC  was tapered, with a 100µm opening, 100µm depth, and 60µm bottom. It is lined, rather than filled, and is fabricated from the backside. It was demonstrated for stacked packages.  The example from Leti was also a backside design, with a 70µm top and depth, Cu passivation and UBM on the backside. This is used in CMOS Image Sensors (CIS).  From Delft, Prof. Mita demonstrated a MEMS device packaging scheme that involved TSVs with different aspect ratios. DNP’s TSV has top and depth of 30µm, the TSV is formed post wafer processing, and has been demonstrated in a 7-story memory stack. SEMATECH’s TSV uses a non-Bosch process by a Tokyo Electron etch tool, and achieves a 5µm opening with 25µm.  Another non-Bosch process was used by NECEL for a via first approach with a polysilicon fill for DRAM stacks.

Finally, Mita-sensei talked about aspect ratio dependent etching (ARDA), and the challenges of both Bosch and non-Bosch processes. It was clear from the SEM examples he showed that the non-Bosch process generally results in a tapered via-shape, while Bosch DRIE achieves a much more vertical sidewall. However, scalloping is one challenge of DRIE that occurs when etching rate is increased.  In conclusion, he briefly talked about a rival technology, FEMTO second laser etch, and hinted he was looking for a laser etching tool for his lab in Tokyo so he could report more detailed laser etch results in future.

The afternoon session was shared by etch tool manufacturers, who took the opportunity to explain their companies’ approach to deep silicon etching technologies for Through Substrate Vias, their respective backgrounds in the field, and their special areas.

First up was Kenichi Kikushima from Hitachi High Technologies, who explained the company’s concept for low-cost, scaled-down TSVs using DRIE-specific high speed etching with microwave ECR plasma. The high pressure, high power process reportedly achieves a high etch rate which translates to lower cost due to reduced etching and plasma reactor cleaning time.

Yoshiyuki Nozawa from SPP Technology Process Systems (SPTS) presented the company’s full line of etch and dry deposition tools to demonstrate the capabilities for MEMS and TSV etching and metallization processes offered since the company’s merger of STS and Aviza one year ago, along with subsidiary Primaxx, for vapor etch release processes.  Nozawa-san listed the company’s suite of tools for MEMS processes including Si sacrificial layer etch,  oxidized film anisotropic etch, compound etch, nitridized/oxidized film forming and metal film forming tools.  Tools are intended to take a process from the R&D lab to pilot production through to volume production simply by adding modules.  For 3D TSV processes, Mr. Nozawa presented tools for etching high aspect ratio vias at high etch rates with smooth sidewalls, with no notching at the stop layer because of the oxidized film. Finally, he addressed the metallization capabilities of the company.

Nicolas Launay, R&D director for Tegal France, talked about Tegal’s focus on etch processes using  ICP reactors, and how the company has a significant commercial history and presence in high volume manufacturing TSVs (both through silicon and through substrate variations) in the compound semiconductor and MEMS markets. As an example of this, Launay talked about Silex Microsystems commercial TSV products and services for MEMS, silicon interposer technologies and wafer-level packaging.  Tegal’s goal is to provided tools with reliable handling for a variety of substrates, high silicon etch rates, with high quality sidewall profiles and robust silicon DRIE processes for TSV in high volume manufacturing environments.

To this end, Launay said the company is involved in a number of joint development projects (JDPs)  to develop practical TSV process flows. For example, the Verdi project is focused on developing high density vias for 200 and 300mm wafers with 5-1 aspect ratio vias. Partners in that program include ST Microelectronics, Leti, Ales-Air Liquid, Alchimer, and the University of Savoie.  The Smartstack JDP involves ST Micro, Leti, Gemalto, EMSE, and Fogale in developing a process flow for low density, vertical and tapered vias on 200 and 300mm wafers with aspect rations of 2-1. The 3Dice project focus is to develop high volume, low cost production processes for low and mid-density vias on 150mm wafers with  3:1 to 6:1 aspect ratios targeting telecom applications. Partners include ST Micro, Leti, 3D Plus, Datacon, EV Group, LMR, PVA TePla, Replisaurus and Oerlikon.

Launay noted that for via first, middle and last possibilities, ongoing studies are expected to define one or two additional standard process flows for low-cost, high quality, commercial 3D IC silicon DRIE processes.

The final speaker of the day was Mitsuro Hiroshima, from Panasonic Factory Solutions, who, like the others, stressed the company’s long history in plasma processing that extends back to 1982 and includes silicon, compound semiconductors, MEMS, LEDs, power devices, and TSVs for CIS and silicon interposer technology.

Hiroshima explained the various challenges for plasma processes with TSV etch, and how the company combines Bosch and Non-Bosch process to achieve desired results.  He talked about a TSV “plugging” process (backside grind and plasma etch to reveal Cu TSV plugs)  that achieves a damage-free wafer surface.  Additionally, the Panasonics suite of plasma tools includes dry etching, cleaning, grinding and dicing.  Hiroshima demonstrated the improved result of plasma dicing over blade dicing, and how for thin wafer applications, this option improves chip strength.

While each speaker had something unique to present about their respective offerings, one clarifying point was driven home first by Dr. Mita, and then echoed by each subsequent speaker. Through Substrate Via technology is nothing new, and contrary to popular belief in the CMOS IC-side of the semiconductor industry, has been in mass production for compound semiconductor and MEMS manufacturing for quite some time.   And from these beginnings great things shall arise.


The Bio hasn't been uploaded yet

View 's posts

Become a Member

Media Kit