Guest bloggers from across the supply chain and from various market segments contribute to provide insight on the implications of 3D integration technologies. Industry experts who have something to say are invited to participate.

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MEMS & Sensors Technical Congress Highlights Automotive Market, Emerging MEMS Technologies

This year’s MEMS & Sensors Technical Congress (MSTC), February 19-20, 2019, features a deep dive into the changing automotive sensor landscape, a look at emerging MEMS technologies, and an exploration of integration standards. The more technically focused of SEMI’s annual MEMS events, MSTC returns to Monterey, California, in conjunction with FLEX, the conference that highlights new form fa... »

3D Integration Enables More than Moore Technologies

Looking back at the last 10 years, it is very difficult to choose one single event that was the most pivotal for commercializing 3D integration technology. There have been many prior events that have driven 3D integration and aligned the whole industry in migrating from monolithic 2D to heterogeneous and 3D integration. From my perspective, the most path-breaking event was the rise of the backside... »

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Breakthroughs in 3D Stacked FinFETS and 3D Sequential Integration

The annual International Electron Devices Meeting (IEDM) presents the latest developments in electronic device technologies focused on advanced scaling, heterogeneous integration, quantum computing, and wide bandgap devices. Among several excellent papers on 3D integration were two papers on 3D sequential integration, long the holy grail of 3D integration because of the promise of up to 50% logic-... »


3D ICs Eliminate the Memory Wall

The adoption of 3D ICs allowed the elimination of the “Memory Wall” using a new memory architecture and through silicon via (TSV) technology. While individual ICs became faster with each process node, the communication between the chips was constrained by limited pin counts, power hungry I/Os, and PCB-space limitations. Assembly of multiple dies into one package enables extremely wide busses b... »

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Probe Test for 3D Integration: A Thousand Mile Journey

When we look back at the last 10 years, it’s really been a series of baby steps to move the commercialization of 3D integration technologies forward. There is no single pivotal event that catalyzed the 3D evolution. Like the Chinese philosopher, Lao Tzu said, “do the difficult things while they are easy and do the great things while they are small. A journey of a thousand miles begins with a s... »

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3D Powered: From Image Sensors to Artificial Intelligence

The widespread deployment of 3D stacked CMOS Image Sensors (CIS) in consumer electronics, namely smartphones, by handset makers domestic (Apple, iPhone) and overseas (Samsung, Galaxy), is certain proof that 3D integration technologies pivoted over the last ten years from being something useful only for fairly esoteric applications and high ASP products, to being a technology that reached the right... »


3D InCites Turns 10: A Brief Analysis of the 3D Journey

I cannot believe 3D InCites is already turning 10! As wise people say, time flies!  Taking a step back, I have to admit a lot of progress has been made since my first attendance as a young engineer to the EMC 3D workshops back in 2008. At that time, we were discussing how to form a via, how to fill it, how to use a temporary wafer carrier to process thin wafers…etc. We are definitely more m... »

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Advanced Packaging Trends – Part II: Solving Lithography Challenges

Part 1 of this advanced packaging (AP) article series focused on solving photoresist (PR) strip and under bump metallization (UBM) / redistribution layer (RDL) challenges. This article looks at AP trends from a lithography standpoint and proposes solutions to associated lithography challenges. The need for advanced packaging solutions is greater than ever as the world continues to demand increased... »

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Advanced Packaging Trends, Part I: Solving PR Strip and UBM/RDL Challenges

Over the years, the semiconductor industry has relentlessly focused on shrinking gate dimensions to drive performance. This focus has now transitioned to the packaging side as customers are shifting from wire bonding to flip chip for use in wafer level packaging (WLP). According to VLSI Research, about 35% of chips are currently packaged using WLP techniques. Advanced packaging opportunities slowe... »

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European 3D Summit 2018: Fraunhofer Tour and Presentations 

This year’s European 3D Summit in Dresden, which highlighted “Heterogeneous Integration Driving 3D”, was led off by presentations and a lab tour of the Fraunhofer Institute, whose 18 high-performance centers collaborate with companies, universities and other research institutes in Germany.  All pictures and diagrams courtesy of Fraunhofer IZM. The Fraunhofer IZM presentation was introdu... »

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