HYBRID BONDING: FUELING ADVANCED MEMORY AND HIGH PERFORMANCE COMPUTE ROADMAPS
Speaker Laura Mirkarimi, Xperi
Wednesday, July 15, 2020 | 12:00pm-12:45pm Eastern | Online Webinar
The promise of high growth markets for the internet of things and artificial intelligence, is driving semiconductor manufacturers to increase functionality and performance of devices and modules. With Moore’s law losing steam due to the technical challenges and increasing costs, the electronics industry looks toward 2.5D and 3D stacking to meet the market requirements for future products. A central theme for higher functionality is increased bandwidth and finer pitch interconnects. The challenge to deliver low cost modules with high yield remains difficult. For example, High Bandwidth Memory die stacks have thermal performance challenges due to the underfill material between each die. As the number of die stacks in DRAM increases (up to 12 high today), both the yield and thermal performance can degrade using conventional Cu bump technology.
Since the incumbent interconnect technology is unable to deliver a scalable solution for the next generation package, the barrier for adoption of a new technology is lowered. The semiconductor industry is developing hybrid bonding, also referred to as direct bonding. Direct bond interconnect (DBI®) and DBI Ultra are low-temperature wafer to wafer (W2W) and die to wafer (D2W) bonding technologies that reliably achieve interconnect pitches scaled to 2 µm today. While DBI technology has been in high volume manufacturing for several years in W2W application, a reliable die to wafer process is currently being developed across the semiconductor industry (Xperi DBI Ultra D2W). The availability of the D2W technology will enable the fine pitch interconnect to become pervasive in electronics.
The advantage of the DBI interconnect is compared to conventional Cu-Cu and solder interconnect in product roadmaps for advanced memory such as 3D DRAM and 3D NAND, and performance compute devices such as CPU, GPU, FPFA or System on Chip (SoC) will be discussed. Widespread disaggregation and chiplet architecture innovation offer enhanced performance with cost reduction through enhanced time to market and leverage of legacy designs. The cost reduction advantages for adopting this DBI platform technology for (SoC) and memory applications will be discussed.
Test vehicles with bond pad sizes ranging from 10 to 1 um and daisy chains ranging from 30k to 500k links will be discussed. Electrical test results of yield and environmental stress testing performance including temperature cycling and highly accelerated stress test (HAST) will be shared. Finally, die stacking results and hybrid bonding of TSV to the bond pad will be presented.
Speaker: Laura Mirkarimi
Vice President, Engineering – 3D Semiconductor Portfolio and Technologies at Xperi
Laura Mirkarimi obtained her PhD in Materials Science at Northwestern University and her B.S. in Ceramic Engineering at Penn State University. She joined Hewlett Packard Laboratories in 1993 in the Solid-State Technology Laboratory and developed ferroelectric memories, transparent optical conductors for displays, and photonic crystals for all optical circuits and single molecule detectors. In 2005, she joined Tessera Technologies to begin her packaging career working on wafer level packaging, Cu pillar and PoP where she was VP of Design, Simulation and Reliability. In 2015, she joined Zeiss Microscopy Division as their VP and Electronics Segment Marketing Manager. She returned to Tessera, now Xperi, in 2016 as VP of 3D Portfolio and Technology where she leads the engineering team to further develop hybrid bonding for both wafer-to-wafer and die-to-wafer applications. Dr. Mirkarimi holds 43 patents and more than 40 publications.
Registration is FREE for IMAPS members, including student members.
Non-member registration is $50.