Samsung 12-layer memory with 3D-TSV

Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically interconnect the two DRAM chips through more than 60,000 TSVs. Despite the increase in the number of layers from eight to 12, the overall thickness of the package remains at 720 µm so designers will not have to change dimensions to use the new technology (Figure 1). Samsung will soon be able to mass-produce such 24Gb high bandwidth memory (HBM), which will provide 3X the capacity of 8GB HBM on the market today.

The subsequent shorter data transmission time between chips than other bonding technologies results in significantly faster speed and lower power consumption. Reportedly these thin DRAM layers are being achieved with acceptable yields for high-end products. Samsung reports that these 12-layer stacks will offer the highest DRAM performance for applications that are data-intensive and extremely high-speed.

12-layer memory
Figure 1: (L) eight-layer cross-section. (R) 12-layer cross section.

One of the first products to use Samsung’s 12-layer DRAM packaging technology will reportedly be Samsung’s 24 GB HBM2, which will soon be in mass production. These devices will allow developers of CPUs, GPUs, and FPGAs to install 48 GB or 96 GB of memory in the case of 2048 or 4096-bit buses, respectively. It also allows for 12 GB and 6 GB stacks with less dense configurations.

Samsung did not reveal pricing for the 12-layer 24 GB HBM2 devices, but since they will be available exclusively from Samsung, we would expect a significant premium.

We expect Samsung will preset more data in their paper “3D-Stacked DRAM Technology and Function-in-Memory Solution” by, Kyomin Sohn, Samsung at the upcoming IEEE IEDM meeting in Dec. in SF.

HBM Standards

In Dec 2018 JEDEC updated JESD235, the HBM DRAM standard.

HBM is a high-performance RAM interface for 3D-stacked DRAM from Samsung and SK Hynix. HBM DRAM has gained market penetration in graphics, high-performance computing (HPC), server, networking and client applications where the superior peak bandwidth, bandwidth per watt, and capacity per area have significant value. The first HBM memory chip was produced by SK Hynix in 2013, and the first devices to use HBM were the AMD Fiji GPUs in 2015. The HBM standard was adopted by JEDEC as an industry-standard in October 2013. The second generation, HBM2 standard, was accepted by JEDEC in January 2016.

The standard was developed and updated by industry experts from leading GPU and CPU fabricators to extend the system bandwidth growth curve beyond levels supported by traditional discrete packaged memory. JESD235B is available on the JEDEC website.

Standard JESD235B leverages wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into eight independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth making capacities of up to 24 GB per stack possible.

This update extends the per pin bandwidth to 2.4 Gbps, adds a new footprint option to accommodate the expected 16 Gb-layer and 12-high configurations for higher density components. Additional clarifications are provided throughout the document to address test features and compatibility across generations of HBM components.

With this announcement by Samsung, can the 12-layer SK Hynix announcement be far behind?

SHIP Winners

In IFTLE 422 we announced that the Navy (i.e. NSWC Crane) was seeking proposals from US industry participants for the development of technical and business plans to establish a secure on-shore design, assembly, and test capability for high density packaging. This facility is meant to support “…the heterogeneous integration of state-of-the-art (SOTA) commercial integrated circuits (ICs) with defense specific application-specific integrated circuits (ASIC) and Department of Defense (DoD) specific applications leveraging integrated Radio Frequency (RF) and sensor technology”. The design centers will be referred to as the Secure SOTA Heterogeneous Integrated Packaging Prototype Design Center (SHIP-DC) while the manufacturing capability will be referred to as the Secure SOTA Heterogeneous Integrated Packaging Prototype Assembly and Test Center (SHIP-ATC).

The plan was to come up with an advanced packaging production solution that is accessible to the entire industrial base while giving the DoD the ability to more rapidly integrate technologies to modernize our systems. Winners were just announced and include:

  • GE Research
  • Intel Federal
  • Keysight Technologies
  • Northrop Grumman Aerospace Systems
  • Qorvo
  • Xilinx

IFTLE will be following up on the progress of this program as it becomes clearer what each of these winners have committed to do.

For all the latest in Advanced Packaging stay linked to IFTLE………….

Phil Garrou

Dr. Philip Garrou is a subject matter expert for DARPA and runs his consulting company…

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