For the fifth consecutive year, the European 3D Summit returns to Grenoble, January 23-25, 2017. The event has evolved over those years, beginning its tenure as the 3D TSV Summit, then last year re-branded as the 3D Summit in acknowledgment that not everything in 3D has to do with through silicon vias (TSVs).
I’ve been honored to attend the four previous years, and have found the event to consistently deliver quality content, thanks to a very active organizing committee who has paid attention to the trends to make sure the presentations remain right at the edge what’s happening in 3D integration. Additionally, networking and social activities have helped this group foster the collaborative environment needed to bring 3D to commercialization. I spoke with Anne-Marie Dutron, senior director, business development, SEMI Europe, about this upcoming event and what attendees can expect.
“Last year, we extended scope from TSV to 3D, and included dedicated sessions on imaging products and fan-out wafer level packaging (FOWLP),” said Dutron. This made sense, as imaging applications are among the first ramp 3D IC stacking to production in backside illuminated image sensors and wafer-level cameras. Including FOWLP was in anticipation of TSMC’s massive launch of its integrated fan-out package-on-package (InFO PoP) technology, aimed at delivering a lower-cost option to 3D TSVs in mobile applications.
While the expansion was well-received, this year’s agenda will re-focus once more on technical solutions, based on feedback received from last year’s survey responses. Aptly themed: Creating High-density Systems, Dutron says the agenda will address myriad options available to create miniaturized, highly integrated systems, and which choices are suited to which applications.
As the industry shifts focus from Moore’s law to heterogeneous integration to meet current and future computing needs, 3D integration has become the path forward.
“Moore’s law is ending. That is the statement from the industry. Everybody understands that advanced packaging has come through to continue miniaturization while improving performance and keeping cost down,” said Dutron. “This topic will be addressed throughout the conference. System-in-package (SiP), fan-out, 2.5D, and 3D are all different solutions to reach the same goal.”
Dutron also noted that advanced packaging has gained real importance in product design. No longer can packaging be considered as the last step, it’s now part of the whole design to improve system performance. The goal is to provide a balanced perspective of both 3D IC and packaging solutions because the full scope is important. As such, this year’s agenda will focus on the issues and challenges to bridge the gap.
Overall, the 3D Summit will follow a similar format to the previous editions, kicking off with a market briefing on market trends, what technologies have reached high-volume manufacturing, and what is in ramp up. This session will feature a reverse engineering report from System Plus, which will reveal what products have integrated InFO PoP. From Yole Dévéloppement, we’ll here about where 3D integration is going in multiple flavors including chip stacking, through mold via (TMV), fan-out PoP, and more.
As attendees expressed interest in learning about what technical roadblocks and challenges remain, there will be a session devoted to thermal management, featuring current work at research institutes and in research departments to control thermal issues. There will also be a full session devoted to future 3D technologies that will showcase “what’s cooking” in the laboratories that will result in disruptive technologies to solve high-density challenges, such as Si photonics. Application discussions will focus on 3D Integration for automotive and consumer applications, as well as memories and high-performance computing products. 3D equipment manufacturers will present a session highlighting equipment optimization for 3D in HVM.
Other highlights of this year’s agenda, according to Dutron, include keynotes by Xilinx and the National Center for Advanced Packaging (NCAP), and a panel discussion moderated by Jean-Christoph Eloy, Yole Développement. As Xilinx was first to market with 3D in its FGPA products, Xin Wu, VP, Xilinx, will give a review of 3D IC and its application in FPGA products. Wenqi Zhang, Director of R&D at NCAP will provide an understanding of what China is doing in terms of advanced packaging to help attendees understand what China is investing and focusing on in its emerging area of advanced packaging. The panel discussion will feature panelists from an IDM, OSAT, substrate manufacturer, and FPGA provider who will discuss how they are bringing high-density interconnect into production.
This year’s social highlight will be a Gala Dinner, held in Minatec’s expanded facility, the Titanium Room, which will be decorated to match the high-tech environment. Dutron promises fun and relaxing entertainment that will rival last year’s team-building quiz.
With technologies so close to mass production and the industry turning its focus on heterogeneous integration, Dutron says it’s an especially important year to attend the European 3D Summit. “This year’s program will provide insight on what’s next for 3D integration, what the next steps are, and what the next disruptive technologies will be,” she said. “It’s important to see what the trends are and where technology will innovate and create new value and new possibilities for the product designer.”
I couldn’t agree more. My flight is already booked. Is yours? ~ FvT
Based on the few Packaging Conferences in Europe that I have attended, I can definitely say that over there they sure serve classier hors d’oeuvres than the ones we get here.
However when it comes to the innovativeness of R&D, or seeing even a few of them through to even medium volume production, the less said ( eWLB excepted ) the better ! Working with assured Govt. funding makes them less goal driven and a tendency to not do enough rigorous theoretical analyses before getting approval to “cut metal”, seem to be at the root of not making enough significant contribution. This was the case with a whole crowd of greenhorns jumping on to the TSV bandwagon.
But it is good to hear that after about 5 years of this TSVs only orgy in Govt. funded Labs, they are coming around to admit that yields are low even in So. Korea ( after all to stick stacked dies together they did no further innovation but kept on using my 23 year old invention at Motorola for single dies ! ) and costs are high even for HPC ( but perhaps acceptable for Defense / Space, which is where W. Europe was using my Flip Chip Bonding patents at Moto ).
When they finally do get around to stacking FO WLPs ( an outgrowth of not just Infineon work but also that done here in Phx ) to say build there own electronics for self driving cars and find out the issues, our recent work at APSTL ( patents pending ) to obtain nearly TSV like performance ( at least for bandwidth & power consumption, if not quite the form factor ), w/o any TSVs at all, will be there for a theoretically sound and robust low cost solution.