The IEEE S3S Conference (shorthand for the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference; quite a mouthful, I know!) is an annual gathering of an intimate crowd (generally 100-125 attendees) that for 35 years has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulators (SOI) technology. A parallel 3D integration track was added to the conference agenda in 2014, and this year (2016) was the first time I attended, as Zvi Or-Bach, Monolithic3D, asked me to moderate the rump session, Monolithic 3D vs. 3D TSVs. I came in for the panel and stuck around through the first day to catch some of the keynotes and Bob Patti’s 2.5D 2.5/3D Technology and Commercialization presentation.
As with many conferences this year, the overall theme was Energy Efficient Technology for the Internet of Things, and the talks ranged from heterogeneous integration solutions based on both CMOS and III-V technologies to fully-depleted SOI to the long-awaited commercialization of 2.5D and 3D technologies.
During the panel discussion, which turned out to be a cozy gathering of 14 in addition to the five panelists, we set out to solve the mysteries of monolithic 3D. (You can do that with a small group of people.) Panelists included:
- Zvi Or-Bach, CEO MonolithIC 3D
- Paul Franzon, Professor, NCSU & 3DIC 2016 Conference Co-Chairs
- Eugene Fitzgerald, Professor at MIT & Lead PI, SMART Research Center
- Bob Patti, CTO at Tezzaron Semiconductor
- Arifur Rahman, Intel/Altera & pioneer of 2.5D at Xilinx
Each addressed the question: Is it really a case of monolithic 3D vs 3D TSV? Will one win out over the other? The group was quick to respond collectively that the two approached will co-exist and even complement each other at times. Rahman provided a compelling argument for this: Emerging applications require significant improvements in performance/watt, lower system-level latency, and shorter time-to-market. Additionally, diverse markets need scalable 3D IC technologies that:
- Moderate thermal envelope (5-10W) to high-performance (100-150W+) applications
- Enable integration of memory stacks and logic-memory
- Allow for heterogeneous integration capabilities
Fitzgerald offered the caveat that to achieve highest growth potential, monolithic 3D designs must originate in both CMOS and III-V materials. He said there is no monolithic future for Si by itself, hence the focus on packaging, TSVs, etc. However, 3D TSVs are restricted by die size (Figure 1).
Settling on a definition for monolithic 3D, to begin with, was when things got controversial.
Or-Bach defined monolithic 3D as 3D IC with single crystal channel multilayers, interconnected by through layer vias < 200 nm and a via pitch < 400nm. He identified 3D NAND as a monolithic 3D device that is already in high volume and predicted that 70% of transistors will use this approach in 2017. He also said this technology can be extended into other memory structures, as well as logic.
The audience challenged (rather loudly – this was the rump session after all, and the bar was open) Or-Bach’s classification of 3D NAND as a monolithic 3D structure; 3D yes, monolithic, no. We settled on defining monolithic 3D as that which is built using sequential layer processes (CEA-Leti’s CoolCube and Tezzaron’s DiRAM qualify).
The question arose; can monolithic 3D be used for heterogeneous integration? Or-Bach and Fitzgerald both said yes. In fact, Fitzgerald believes that a monolithic 3D approach offers the lowest cost through interconnecting high density of active devices. Indeed, he said “sprinkling” III-V devices (such as LEDs, MEMS, through the CMOS in a monolithic approach will achieve the most value.
After listening to the keynotes, I got the impression that there are two teams vying for IoT supremacy: Team SoC and Team heterogeneous integration.
Nick Yu, Qualcomm, set the tone for finding IoT solutions by talking about the company’s plans for advancing its wireless technology roadmap beyond just 4G to 5G. Since 4G is expected to continue through 2020, Qualcomm’s intent is for 5G to leverage investments of 4G, so that devices are backward compatible with 4G, as we need to accommodate the global wireless infrastructure. With regard to homogeneous vs. heterogeneous architecture, Yu said that everything we do is heterogeneous, as there are different bands in different countries. “Advancing 4G LTE requires heterogeneous networks, interference management, carrier aggregation, and new features,” he said. And to that end, we need system integration. “Devices, machines, and things are becoming more intuitive because of sensor integration,” he added. “It may not make sense to integrate into SoC, we need to find ways to heterogeneously integrate them.” Yu cited Xilinx FPGA on silicon interposer technology, as an example of successful heterogeneous integration. He also said that since 2009, Qualcomm has relied on the package on package (PoP) as the most cost-effective heterogeneous configuration for stacking logic on memory.
Regardless, Team SoC remains confident that the needs of IoT devices can be met using FD-SOI technologies. “No exponential is forever but forever can be delayed,” noted Ron Martino, NXP. For him, the elixir of SoC life is FD-SOI.
Rooting for Team 3D, was Bob Patti, who talked up interposer and 3D options as the most cost-effective, readily available, and versatile approach with limitless possibilities for design. “Moore’s Law has died of old age,” says Patti. “It’s time to move on.”
As Patti noted, sure, heterogeneous can potentially be done with FD-SOI, but why invest the cost and time to develop it, when 3D technologies are ready to roll? It reminds me of where we were 10 years ago with a technology looking for an application. As long as we could continue scaling or using incumbent packaging technologies, 3D got pushed out, even though it was feasible. Also, Patti reminded me, back then packaging just wasn’t as sexy as scaling. Now, however, with the end of Moore’s Law, it’s the sexiest thing the industry’s got going. ~ FvT