Will 2.5D and 3D Stacking Save the Semiconductor Industry?

Will 2.5D and 3D Stacking Save the Semiconductor Industry?

Year’s ago, when I was managing editor of Advanced Packaging Magazine, each January issue featured an industry forecast cover story. For several years in a row, that issue predicted advanced packaging would be the key to improved performance at lower power and lower cost. January of 2007, we declared “Packaging Saves the World!” and in January of 2008, the cover story was “Packaging Drives the Industry.” Of course this was when the only 3D stacking technology was Package on Package (PoP). 3D ICs were still a gleam in researchers’ eyes, and the term 2.5D hadn’t even been coined yet. Even back then, with the perpetual end of Moore’s Law looming, those in the packaging world were confident that they held the key to improved performance and low power beyond scaling. I can’t help but think these early predictions are coming true, particularly as node shrinks to 20nm and beyond become more challenging, costly and harder to justify.

While some still argue that 3D ICs may never happen for a variety of reasons (remaining technical challenges, cost, redesigning hardware to accommodate through silicon vias (TSVs)), others report that we are on the brink of commercialization for DRAM memory stacks (note: the memory stack of the Hybrid Memory Cube (HMC) and HBM DRAM from Hynix are 3D ICs) and that the ultimate “holy grail” of 3D heterogeneous integration, where advanced semiconductor materials and different functions is combined with high-density silicon CMOS technology, is coming sooner than expected. Still others keep moving the bar on what constitutes HVM. I read one comment that it would be “limited to the handheld market.” Which is not limiting at all when you consider the size of that market. (Come to think of it, the DRAM market is no small potatoes either. Just as Mircron and Hynix.)

One argument that I really don’t get is that the definition of 3D IC makes it difficult to determine if/when its in volume manufacturing. I guess that for those who have spent their semiconductor careers focused on chip design, where the nomenclature is straightforward, and technology is defined by numbered nodes, whether or not a specific node is in volume production is clear. For them, the variety 2.5D and 3D configurations being developed must indeed be baffling. But does it really matter if we’re talking about 2.5D, 3D IC, or 3D system-in-package (SiP)? I don’t think so. What matters is that as a whole, 3D integration technologies leverage vertical integration and shorter interconnect paths to provide packaging solutions for whatever performance gain is required, at a lower cost than scaling to the next node.

Even Intel is embracing the concept as it announced its Embedded Multi-die Interconnect Bridge (EMIB) for its 14nm foundry customers. According to a press release, this is a lower cost and simpler 2.5D packaging approach than silicon interposers with TSVs for very high density interconnects between heterogeneous dies on a single package. It involves embedding a small silicon bridge chip into the package, enabling very high-density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost. Does this count as a 2.5D package if there aren’t TSVs? Intel clearly thinks so.

Let’s just think about it for a minute. The semiconductor industry is notoriously conservative (thus the long drumroll to 3D). If 2.5D and other 3D integration technologies weren’t poised to save the industry, would all the major foundries and OSATS be playing this giant game of Chicken to see who blinks first? Would the major front-end equipment suppliers — who were only too happy to leave the middle-end-of-line (MEOL) process tool development to the advanced packaging equipment suppliers — be throwing their hats into the ring now if HVM of 2.5D and 3D ICs weren’t imminent? That’s a pretty big gamble to take, particularly in the wake of the EUV lithography and 450mm transition push-out. Deep inside, everyone knows 3D integration the right way to go. The fact of the matter is, its really already happening. I can’t wait to say I told you so! Oh wait, I think I just did. ~ F.v.T.