Year’s ago, when I was managing editor of Advanced Packaging Magazine, each January issue featured an industry forecast cover story. For several years in a row, that issue predicted advanced packaging would be the key to improved performance at lower power and lower cost. January of 2007, we declared “Packaging Saves the World!” and in January of 2008, the cover story was “Packaging Drives the Industry.” Of course this was when the only 3D stacking technology was Package on Package (PoP). 3D ICs were still a gleam in researchers’ eyes, and the term 2.5D hadn’t even been coined yet. Even back then, with the perpetual end of Moore’s Law looming, those in the packaging world were confident that they held the key to improved performance and low power beyond scaling. I can’t help but think these early predictions are coming true, particularly as node shrinks to 20nm and beyond become more challenging, costly and harder to justify.
While some still argue that 3D ICs may never happen for a variety of reasons (remaining technical challenges, cost, redesigning hardware to accommodate through silicon vias (TSVs)), others report that we are on the brink of commercialization for DRAM memory stacks (note: the memory stack of the Hybrid Memory Cube (HMC) and HBM DRAM from Hynix are 3D ICs) and that the ultimate “holy grail” of 3D heterogeneous integration, where advanced semiconductor materials and different functions is combined with high-density silicon CMOS technology, is coming sooner than expected. Still others keep moving the bar on what constitutes HVM. I read one comment that it would be “limited to the handheld market.” Which is not limiting at all when you consider the size of that market. (Come to think of it, the DRAM market is no small potatoes either. Just as Mircron and Hynix.)
One argument that I really don’t get is that the definition of 3D IC makes it difficult to determine if/when its in volume manufacturing. I guess that for those who have spent their semiconductor careers focused on chip design, where the nomenclature is straightforward, and technology is defined by numbered nodes, whether or not a specific node is in volume production is clear. For them, the variety 2.5D and 3D configurations being developed must indeed be baffling. But does it really matter if we’re talking about 2.5D, 3D IC, or 3D system-in-package (SiP)? I don’t think so. What matters is that as a whole, 3D integration technologies leverage vertical integration and shorter interconnect paths to provide packaging solutions for whatever performance gain is required, at a lower cost than scaling to the next node.
Even Intel is embracing the concept as it announced its Embedded Multi-die Interconnect Bridge (EMIB) for its 14nm foundry customers. According to a press release, this is a lower cost and simpler 2.5D packaging approach than silicon interposers with TSVs for very high density interconnects between heterogeneous dies on a single package. It involves embedding a small silicon bridge chip into the package, enabling very high-density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost. Does this count as a 2.5D package if there aren’t TSVs? Intel clearly thinks so.
Let’s just think about it for a minute. The semiconductor industry is notoriously conservative (thus the long drumroll to 3D). If 2.5D and other 3D integration technologies weren’t poised to save the industry, would all the major foundries and OSATS be playing this giant game of Chicken to see who blinks first? Would the major front-end equipment suppliers — who were only too happy to leave the middle-end-of-line (MEOL) process tool development to the advanced packaging equipment suppliers — be throwing their hats into the ring now if HVM of 2.5D and 3D ICs weren’t imminent? That’s a pretty big gamble to take, particularly in the wake of the EUV lithography and 450mm transition push-out. Deep inside, everyone knows 3D integration the right way to go. The fact of the matter is, its really already happening. I can’t wait to say I told you so! Oh wait, I think I just did. ~ F.v.T.
Francoise
Thanks as always for a great post. Going back to my memory days, I wanted to share a few thoughts with you.
From a memory perspective, it may have nothing to do with the cost of the next node, rather the next density at a discrete level and the cost trade off analysis. For example, today only Micron declares a discrete 8Gb (Gb = Giga Bit). The vast majority are in 4Gb with no rush to go to 8Gb because the costs to design along with the yield loss and curve bringing up the volume production are not supported by the purchases of the end user. In general the end user will utilize a 4Gb based solutions vs. an 8Gb (Even though the 8Gb one will be lower power due to fewer ICs) until it gets close to price parity.
For example see below released from Samsung just this week on DDR4.
Samsung mass-produces industry’s first TSV-based DDR4 DRAM module
http://www.pcworld.com/article/2599700/samsung-starts-production-of-3d-ddr4-dram-modules.html
This is a 64GB (Giga Byte) Registered DIMM. It has 144pcs of 4Gb (Giga Bit) ICs stacked in sets of 4 High via TSVs. The cost of an 8Gb based 64GB module using 72pcs of 8Gb stacked only 2 High would be deem too costly from the end user due to the premium of 8Gb to 4Gb (not at parity).
On the 3D historical timeline you mention that 3D IC started in the 2008 with PoP, but I think it goes back further. Back in 2003 or 2004 Elpida was the first memory supplier in the world with the ability to manufacture and qualify a 1GB (GB = Giga Byte) SoDIMM (Small Outline, Dual Inline Memory Module) The reason they could do this was via their proprietary die stacking (at the silicon level) solution called TCP (Tape Carrier Package). For me personally, based on whatever definition anyone wants to apply to 3D IC, I would consider that a 3D solution as it was not packaged die stacking, it was vertically integrating 2 Silicon Die on top of each other and then they sealed the module with a custom designed heat sync for thermals & to protect the IC’s. It was a technology that was designed at what was then Akita Elpida, which is now all under Micron.
Lastly, like how you incorporated the foundry and OSATS. In line with your mention of the Intel advanced packaging article, see below link to a great interview from Dan Hutcheson with Intel VP of Foundry. Some great insight into their approach to supporting 2.5/3D from within their foundry business unit.
http://electronics.wesrch.com/wequest-EL1QIXV-intel-custom-foundry
Rick
Hi Rick,
Thanks for the additional insight. I also forgot to mention the now-famous Samsung 2Gb NAND stack that used TSVs http://www.dailytech.com/Samsung+Announces+3D+Chip+Packaging+Technology/article1761.htm
as well as its wire-bonded 16 die stack for 8Gb NAND flash chips http://www.dailytech.com/Samsung+Develops+16Chip+Stack+Package+Memory/article4797.htm.
Both were introduced in 2006, and have appeared in Powerpoints ever since. Interestingly, even back then, the thought was that 3D stacking would not be suitable for DRAM or other applications as The Daily Tech story notes “…3D packaging isn’t the best route for chip assembly. On relatively slow NAND modules, the thermal envelope is not a huge factor. High speed DRAM, on the other hand, has much higher operating temperatures and will not likely adopt Samsung’s WSP or other 3D packaging in the near future.”
It only took 8 years to work out the kinks to change that. So its no surprise that Samsung would be the first to announce production of a TSV-based DDR4 DRAM module.
Thanks for that “tip of the hat” to history, Francoise.
I observed in a column written a few years back, that if one stands beside the “carousel of innovation”, one is bound to see the same horse come around again. It might be painted a different color or have a different saddle on it but it is essentially the same horse.
In that regard, one will find that memory cube variations were built for military products in the1990s by Dense-Pac and others. The Intel bridge connection concept reminded me of what we promoted at Silicon Pipe a decade ago. TSV concepts go back to the late 1970s and early 1980s by HP and others. Paraphrasing Santayana: “Those who don’t study history are bound to repeat it”
What make news presently is when opportunity to make significant, wide use products (read that as significant revenue) is on the near horizon. The first to conceive of a product or technology are typically not the ones that enjoy the success but they do lay an all important foundation. To that end, look for an end of the use of solder for electronic assembly in another 10 years or so. The economics are simply too compelling to ignore.
Thanks again, Francoise
Best wishes and regards,
Joe
Joe,
As one of the industry’s true advanced packaging pioneers, it’s so great to have you contribute your observations to this blog. We often hear at conferences how today’s 2.5 interposer technologies are really what was called multichip modules (MCM). Too often though, the MCM of yesterday is pointed to a technology that didn’t take off and that “we already tried this.” Its nice to know there were those saw the potential in TSVs and persevered with the development required to take it through to this point of production.
Best Regards,
Françoise