To date we at Mentor Graphics have seen a handful of 3D IC design releases, and even more customer evaluations. However, the predominant driver seems to be a desire to understand the space in case their company elects to move into the space. In general, the perception seems to be that the costs for the current offerings are higher than expected. Moreover, many companies are still trying to determine which products would benefit from pursuing 2.5D/3D IC. Memory-on-memory, image sensor-on-logic, MEMs-on-logic, and memory on SoC/CPU/GPU/FPGA still look like the early contenders.

From our point of view the technical issues related to design, verification and test tools have been solved or are as far along as they can go without additional learnings from volume production. Mentor has physical design (Olympus-SoCā„¢) and physical verification (CalibreĀ®) tools that are ready today to handle 2.5D designs with silicon interposers, and full 3D IC design using through silicon vias (TSVs). This includes generating I/O pin-outs for multi-die configurations, routing on backside metal and silicon interposers, physical alignment checking between dies and LVS connectivity checking across external interconnects. We are working with the major foundries to refine the models for TSVs and these are already integrated into our extraction tools. Moreover, our products are a core component of the 2.5D and 3D reference flows announced by various foundries including TSMC.

In the area of design for test and manufacturing test, our Tessent silicon test suite is 3D IC ready with the capability to route test patterns to multiple stacked dies using standard test control protocols. Designers benefit from the fact that they can use the same patterns created for individual die to test the assembled stacked die package. Cell-aware testing helps improve the confidence in known good die at the wafer level to help reduce the cost of failures in multi-die packaged configurations. We have also introduced hierarchical test to help manage the complexity of testing multi-die packaged systems. ~ J.S.

Joseph Sawicki

Joseph Sawicki is the vice president and general manager of the Design-to-Silicon division. An expert…

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