2.5D Interposer wafer - TSMC

So SPIL’s offering a turnkey model for 2.5D interposers, including fine-pitch fabrication of the interposer wafers themselves? This is certainly an interesting turn of events, particularly with TSMC’s recent announcement that they’re not married to the turnkey model and are willing to collaborate with OSATS. SST’s Phil Garrou got the scoop this week from SPIL’s Mike Ma, at the Confab.

Reporting back from this year’s IITC 2013, held in Kyoto Japan June 13-15, 2013, Rambus’ Deepak Sekar and IBM’s Vincent McGahay contributed a technology round-up on interconnect challenges that was published here in Solid State Technology. In the 3D integration segment, the authors note that papers in this area reflect a trend that 3D is “moving from concept to implementation phase.” They summarize a paper by Ho-Young Son from Hynix, who honed in on stress to transistors caused by TSVs. Son says the company has had success in optimizing processes to achieve reliability. Also of interest, 3D stacking has made it into Tohuku Univerisity’s prototypes for Spin-Transfer Torque MRAM (STT-MRAM). The prototypes reportedly comprise 90nm CMOS technology as well as 2232 TSVs and microbumps.

Thermal issues in 3D ICs is one of the remaining technical issues for 3D IC adoption. iMicronews recently devoted one of its “closer look” pieces to IBM’s work developing a test vehicle to address thermal resistance in 3D chip stacks. The experiment measured temperature at various levels in the chip stack. They found that lower chips in the stack are hotter, presumably because they are farther from the heatsink. The researchers surmised that higher temperatures in a zone are believed to be due to variations in the thickness of the TIM layer. The temperature difference between adjacent chips increases as the pitch of the microbumps is increased. More findings are reported here in the full story.

Other 3D IC related tidbits that I found interesting include an announcement by Austrian chip maker, AMS, that they will integrate through-silicon via (TSV) 3D IC fabrication technology into its ambient light sensor devices for use in smartphones and cameras.
Earlier this spring, nVidia announced its next GPU Family, Volta, will use TSVs to interconnect stacked DRAM to the GPU. Target release date: 2016. Yes indeed, the implementation phase is firmly upon us. Won’t be long now. ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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