2.5D Interposer wafer - TSMC

TSMC calls them 3D Super Chips. The rest of the industry calls it 3D heterogeneous integration. Whatever way you slice it, either 2.5D or 3D IC, it requires TSV technology for its method of interconnect. Here are a few recent items about the latest progress in the march to commercialization of both 2.5D and 3D ICs.

EE Times journalist, R. Colin Johnson recently scored an exclusive interview with TSMC’s CTO and VP of R&D, Jack Sun, who talked not only about the company’s work in CMOS, but about the importance of its 3D IC developments.  Sun emphasized that in TSMC’s opinion, 3D ICs are not just a high density alternative to CMOS scaling but also “a means of delivering super-systems that move beyond system-on-chip (SoC) to systems of diverse integrated technologies” (aka: 3D heterogeneous systems). He goes on to outline the company’s three main focus areas: pushing monolithic CMOS as far as possible; advancing specialty technologies like analog and mixed signal; and 3D TSV technologies (interposer and logic) that tie it all together to create what Sun calls “system super chips.”

According to an April 13 blog post summarizing TSMCs 2013 Symposium by Cadence’s Richard Goering, TSMC reports “excellent results”  with its 2.5D silicon interposer Chip on Wafer on Substrate (CoWoS) technology (in house yields are high), and “promising developments” in true 3D stacking (demonstrated vertical stacking at 28nm). Additionally, a project involving SoC and stacked DRAM is reportedly in the works. Leaving no stone unturned, TSMC is also intrigued with fan-out wafer level packaging, which Sun called “a cousin” to of the silicon interposer. Goering reports that TSMC has qualified for WLP production. It sure seems like TSMC is ready to go head to head with the OSATS on advanced packaging technologies across the board.

On the R&D side, the latest issue of Future Fab International featured a paper co-authored by a team from IME that demonstrates fabrication and characterization of a large size 2.5D through silicon interposer (TSI) in a 300mm processing line targeted for heterogeneous integration.  The impetus behind this work was to circumvent some of the “3DIC bottlenecks” that still need to be worked out, and develop a way to address the challenges in versatile memory and logic system integration.

Phil Garrou also summarizes the processes used in the FFI paper in his latest IFTLE blog post, Scroll past this to find his report on a presentation delivered at ICEP in Osaka Japan, by Urmi Ray, Qualcomm. The punch line – Ray predicts we will see 2.5D and 3D in our phones “soon” and that there are no technical show stoppers for wide I/O Memory on Logic.

Lastly, I was glad to discover Richard Goering’s coverage of this year’s 3D Panel at EDPS 2013, which I was unable to attend. In a post published on Pro Solid Design, Goering talks about the practical tone the EDA experts took in approaching some of the challenges the industry faces with 2.5D and 3D IC packaging. Speakers from Mentor Graphics and Cadence talked about their company’s approaches. Mike Black from Micron gave an update on the Hybrid Memory Cube.

Goering touches on some key-takeaways from the panel including the importance of yield and redundancy; the emergence of stress and design rules for TSVs; an R&D budget problem on the assembly side; progress of thermal management solutions; power management; and general status of the technology. Goering’s final take? “TSVs are hard. It’s been a real tough go but it looks like we’ve got a handle on it,” he concludes. ~ F.v.T.


Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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