At last week’s 3D Test Workshop in Anaheim, CA, I had the pleasure of moderating a panel of industry experts, analysts and bloggers, with a topic focused on 3D ICs, Hype vs. Reality? Jan Vardaman (TechSearch International), Herb Reiter (eda2asic) Paul Werbaneth (executive marketing consultant) and Ira Feldman (Feldman Engineering) joined me in the preparation and execution of what turned out to be a very lively discussion, with lots of participation from the attendees. In fact, I never even had to resort to my prepared questions.
Werbaneth established the framework for the discussion by explaining the concept of the hype cycle using the cast of the Big Bang Theory to illustrate his point (really, you had to be there). Essentially, every emerging technology goes through this cycle some make it, some don’t. The figure here explains it best. First there’s a technology trigger; in the case of 3D ICs it was the emergence of TSV technology. It rapidly climbed the curve to reach the “peak of inflated expectations” getting lots of press and attention on the semiconductor conference circuit. (Heck, even today, any topic with 3D ICs, TSVs 3D Packaging, or 2.5D packaging in the title is bound to fill a room). Then, as the expected adoption date was continually pushed out due to a laundry list of technology and logistical challenges (thin wafer handling, design tools, test, supply chain, yields, cost) 3D ICs plunged to the trough of disillusionment, which for some technologies is known as the Chasm of Death – from which there is no return. The technologies that make it through here, as 3D ICs seem to have, then go through the long slow climb known as the “slope of enlightenment” to reach the “plateau of productivity.”
After Werbaneth’s explanation, I queried both the attendees and the panel, where is 3D ICs on the hype cycle? The consensus is that 3D ICs are climbing out of the trough of disillusionment and starting the long, arduous climb up the slope of enlightenment. (I was slightly surprised by this – thinking we’re closer to the plateau of productivity based on the roadmaps of TSMC, Global Foundries and a number of the OSATS – but then again I tend to err on the side of optimism.) The key take-away from the Hype Cycle discussion is this: we’ve come to the point where real work is being done to overcome the remaining challenges of 3D ICs. We know that at some point, this technology will become critical to future needs, and therefore is well worth the investment to bring it to market.
The ensuing discussion focused mainly on two key questions posed by attendees. One was “Who do we need to convince to get this done?” Feldman provided his answer by describing a recent interaction he had with a colleague who works in a large data center. His (the data center guy’s) reaction to 3D ICs was that the technology seems great, but it’s nowhere near ready. He said they would never risk it until the reliability has been proven. This was a pretty significant encounter, in my opinion, since data centers have been pointed to as a key driver application to HVM. That was one strong dose of hype vs. reality.
However, I’m not sure we fully answered the question: who do we need to convince? The chip designers? The OEM manufactures? The fabless companies? At some point, someone will have to pull the trigger to put this ball in motion.
Another comment that garnered discussion was the need for capital infusion. Herb Reiter talked about recent discussions he’d had with Wall Street VC’s and how they are more interested in dumping money into social media start-ups than they are in 3D ICs at this point, because it’s a quick return on investment, while the 3D IC story lags on.
We also spent a good deal of time talking about the emerging supply chain models, and what we thought of TSMC’s intent to be the one stop shop. Here, Jan Vardaman and Herb Reiter disagreed. Vardaman has consistently voiced her concern about this model, and how since TSMC is not a memory manufacturer or supplier, its not going to be the preferred model for customers looking to manufacture wide I/O DRAM on logic devices. Reiter disagreed, and felt that many customers prefer TSMC’s approach because it takes care of the liability issue.
Now, here I have to add the disclaimer that it’s not easy to simultaneously moderate and editorially cover a panel. I did not take notes, so what you’ve read here is what glued itself to my memory. I’m hoping I got it mostly right, but I invite the panel to add their comments to this post to provide the full perspective. Also, please feel free to correct me if I quoted you in error! I look forward to continuing this discussion in the virtual space. To be continued… F.v.T.
Francoise,
Many thank for putting together an excellent panel discussion. It was a lively discussion and I had lots of fun. I suspect we could have gone on for another hour if we hadn’t already run late for lunch.
In terms of Supply Chain, I think TSMC and others should do well to remember Cesar Ritz’s moto “Le client n’a jamais tort” (or to us Americans: the customer is always right). I think there will be several different scenarios on who supplies what basesd upon the customer’s desires.
And I agree, it is too hard to participate and take notes at the same time. Let’s see what others have to say.
Thanks,
Ira
http://www.hightechbizdev.com
Regarding #1
Hi Ira,
I would assemble this particular panel again any time! I think we all had fun, incuding the audience!
I agree with your comment on TSMC and the supply chain. I think the industry would do best if it can support several supply chain models because the customers needs (capacity, multisourcing memory and silicon, etc) will differ. The supply chain issue shouldn’t really be holding back production if the liability issues can be sorted out, and why can’t that be on a case by case basis?
How about this Ira:
お客様は神様です (Okyakusama wa kamisama desu.)Not only is the customer always right, the customer is a god.
I like the idea of competition along the supply chain. Maybe some customers will prefer one-stop shopping, and maybe others won’t. It seems like at this stage of the 3D IC game both options exist, which means more engines of innovation working to the future benefit of all.
Nobody ever got fired buying from TSMC (?), but where would customer price leverage come from in a one-shop world?
3d IC stacks with TSVs will go into production ONLY when there is no other better / easier method left to get the desired system ( electrical ) performance. This is regardless of availability of infrastructure. If there is a strong need for it then the IDMs can still develop internal capability in less than 1.5 years ( technically it would be orders of magnitude easier than getting into even coarse nodes like 45 nm ). But if there is n’t, then regardless of how many tempting offers the Foundries put out, and how many Conferences push this rather simple-minded “Popular Mechanics” type approach ( that ends up requiring far too many new / disruptive technologies ), there will be no takers,
Using these boundary conditions the migration path is obvious : integration of heterogeneous technology chips where short interconnect lengths matter ( Ex : image sensors / processors ), defense / high end ( i,e. cost be damned ) applications ( Tezzaron ), servers ( improve processor – memory bandwidth ).
So volume consumer electronics – perhaps only much later
As to 2.5 D expect to see volume application next year ( 22 nm processor & DRAM for cache memory on Si substrate )
Hi Francoise,
I am far from being sufficiently involved in this industry to answer your key question, but I just wanted to point out, for what it is worth, that the current (actually 2011) Gartner Hype Cycle graph shows TSVs in about the middle of the Slope of Enlightenment, closer to the Plateau than the Trough. Now the Gartner analysts may or may not know any more than anyone else; that is just what they came up with.
According to the definitions accompanying this graph, one characteristic of this position is that “methodologies and best practices are developing”; and somewhere between 5 and 20% of the potential audience has adopted it.
Hi Jayna,
Thank you for the additional information about the Gartner Hype Cycle graph and the status of TSVs. As you said, “Now the Gartner analysts may or may not know any more than anyone else; that is just what they came up with.”
That’s why it was so interesting during the panel discussion at the 3D Test Workshop to solicit, and receive, a crowdsourced perspective on where 3D IC / TSV is on the curve. It was a tough audience, at least in the sense the many learned opinions offered were a little less rosy than what Gartner said about TSVs in 2011, but the wisdom-of-crowds consensus was that 3D IC technology is definitely emerging from the Trough of Disappointment, not stuck there to die.
Which is a good thing.
Regarding #5
Jayna – Thanks for providing that information. Good to know my optimistic perspective is shared by Gartner.
Regarding #4
Hi Dev,
Thanks for sharing your view of 3D TSV technology with us.
I find your comment: “3D/TSV will ONLY go into production if there is no better/easier way to get to the desired system performance.” very insightful and like your SYSTEM perspective. The best opportunity for IC vendors to grow is to provide system-level solutions.
However, I sense some skeptic in your capitalized “ONLY” and want to share some observations I made in the last ~ 40 years. I have been closely involved in rolling out FPGAs, ASICs in bipolar, CMOS and SOI as well as arrange of new IC design tools and methodologies. Since 2008 I am focused on 2.5 and 3D technologies.
– Our engineers always found ways to make new products better, faster, lower cost and easier to use. Typically much faster than we expected.
– As soon as competitive systems were utilizing the benefits of a new technology (I admit: at initially higher cost) the competitors rushed to follow.
– Every new technology forced some re-aligning of resources. The earlier companies were able to adjust, the bigger the benefits they reaped.
In my view the biggest benefit 3D technology offers our industry is modularity and with it specialization, economies of scale, shorter time to market, lower development cost — and eventually lower unit cost.
Just like the eco-system that allows the automotive industry to sell reasonably priced cars to the consumer and adapt to market needs quickly, the semiconductor industry will build an eco-system where die-level IP (processors / memory / SERDES / Analog- and RF blocks…) will be combined in a die-stack to compose a (sub)system.
Yes, it took the automotive industry a long time to get to today’s cost-effective eco-system. The semiconductor industry will adapt much faster. We have excellent engineers and visionary management.
Thanks for following this long comment…Herb