I keep reading about the various ways chip designers can achieve the performance/power benefits required for next generation mobile devices, and it always come down to two choices; continue traditional CMOS scaling or 3D die stacks. While there are issues with each, it seems that for the designer, the decision is between the devil you know vs. the devil you don’t know.
As processes are in place for 3D stacking, while the EUV lithography necessary to achieve optimal feature sizes at smaller nodes is still not available (and keeps being pushed out) it would seem that the choice to focus on would be an easy one, but apparently not. In his blog post “Where does it Hurt?” Ed Sperling explains why designers are still reluctant to embrace die stacks.
Although reducing feature sizes becomes more technologically challenging and costly, Sperling notes that with die stacking, the “ the big challenge is dealing with a blank slate. Best practices don’t exist yet, which means the opportunity for experimentation—and to get something wrong—are enormous.” In this post, Sperling mentions other areas of pain besides design (architecture) such as ecosystem interaction and cost. He spoke with industry experts (from Open Silicon, Atrenta, Sonics, TSMC and ST Micro electronics) to get feedback in all areas and identify particularly painful areas and came up with responses such as too many choices, too little information, overall lack of experience across the ecosystem, and disagreement about who’s responsible for what.
It seems to me that once someone (anyone?) takes that leap of faith and starts writing on that blank slate, all these apparent hurdles will disintegrate (or in more technical terms, be engineered out). In other words, with 3D, it’s just a matter of DOING IT.
EUV problems may not be so easily solved. In Rick Merrit’s (EE Times) report from the 2012 International Symposium on Extreme Ultraviolet Lithography in Leuven, Belgium, he delivered this verdict: “Moore’s Law, the engine of semiconductor innovation for decades, is losing steam due to delayed introduction of next-generation extreme ultraviolet lithography.“ The primary reason for the delay is of critical technology importance: the light source needed to pattern 14nm chips (“20 times more powerful than the ones used today,” reports Merritt) won’t be available until at least 2014. Merritt also reports that while less powerful sources have been successfully implemented in R&D (at imec) system throughput is still too slow to suit the needs of commercial chipmakers.
Personally, if I was and IC designer, I’d hedge my bets and embrace designing 3D ICs vs. trying to simply continue reducing feature sizes, because at the end of the day, doesn’t it make more sense to design something that can actually be built rather than something that looks great in theory, but is currently not possible to achieve? ~ F.v.T.