Wanted: Alternatives to TSVs

Well this news took a bit of the wind out of my sails this week. I received a press release from TechSearch International titled Manufacturing and Business Issues Push Out Adoption of 3D TSV:  Companies Seek Alternatives for 3D TSV. I like Jan Vardaman, TechSearch’s CEO, and when we meet up at industry conferences, I’m eager to get her perspective on the progress of 3D technologies. She’s a realist, and she knows her stuff, which is what made this news an even bigger bummer for me. Here it is:

Based on analysis of the 3D TSV market and alternatives such as package-on-package (PoP) and 2.5D (which I would argue IS a TSV technology albeit with interposers), TechSearch reports that “while the drivers for 3D ICs remain constant, the time line for its adoption keeps shifting out into the future.  Several technical challenges and infrastructure issues such as business logistics are delaying the full commercialization of TSV technology for 3D ICs.”  Remaining technology issues cited in the report are:

  • EDA tool availability including the ability to use thermally aware tools and the ability to communicate between tools
  • Manufacturing yield in key process steps such as debonding during wafer thinning
  • Thermal dissipation and cooling methods
  • Test methodology

The only one I find surprising is the EDA tool availability, as Cadence reports readiness in this area. The rest are not surprising to me, particularly in the thermal and test areas. Remaining business related hurdles cited in the report include:

  • Infrastructure related issues, including logistic supply chain handoff
  • Reliability data for a broad range of applications
  • Unit device cost compared to alternatives

The report summary also goes on to say that once the technology challenges are resolved and cost-effective solutions are in place, the remaining business model struggles between the foundry and assembly houses regarding who will handle assembly and test could also throw a monkey wrench into all of this. It even goes as far to say that any ONE of these issues could limit full 3D TSV implementation. (Which makes me want to shout, “Get it together people and figure this out! Don’t let a silly thing like competition  stand in the way of such a huge technology enabler. This industry NEEDS 3D ICs!”) As such, companies are seeking alternatives packaging assembly solutions until these issues are resolved.

As I stated earlier, I have a great deal of respect for TechSearch’s work, and although I know they tend to run on the conservative side with their analysis, they’re pragmatic reporting is often right on the money. But still, I’m having a hard time accepting this, because from where I sit, I see a lot more promise, and lots of understanding emerging about the value-added benefits of 3D ICs from a system level approach. But then again, I’ve been drinking the 3D TSV Kool-Aid for a long time. I can only hope that this report turns out to be drastically wrong, and that 3D will be realized at its full potential in the next few years.

In the mean time, while this is sobering news for many, it also opens windows of opportunity for companies like Invensas, who’s sweet spot is what they call the ‘bridge technology’ space, with solutions in place to fit the memory and memory-on-logic PoP needs until 3D is ready. ~ F.v.T.