For most of July I focused on coverage of SEMICON West in 3D. Today, I thought I’d take a look at what else people were talking about in 3D space over the past few weeks.
The Water Cooling Issue
Two bloggers took on the topic of water cooling 3D IC assemblies as a way to handle the heat. Brian Bailey got the ball rolling in his interview with Madhavan Swaminathan, who wears many hats in the 3D space, among them Director of the Interconnect and Packaging Center (IPC), an SRC Center of Excellence, at Georgia Tech, Atlanta (Brian provided the whole laundry list). Swaminathan has been focusing on the challenge of getting the power in and the heat out of 3D ICs. He said while Xilinx has been successful using TSVs as heat channels in their 2.5D interposer technology because they have access to the backside of the chip. He also said that with wide I/O DRAM on logic, the amount of heat being dissipated is small, so standard thermal management processes work fine. But when you start stacking logic on logic, in true 3D ICs, the heat gets trapped. Pumping water through TSV microchannels has been tossed in the ring as a solution, but Swaminathan says it’s not a viable option. (You can read the full interview here)
Steve Leibson, EDA360 Insider, also referenced this interview in his blog, and stirred the pot by talking about a water-based cooling solution developed by IBM for a 3-petaFLOP supercomputer called the SuperMUC that runs on 3.5 MW of electricity. It’s called Aquasar, which reportedly cuts the energy needed for cooling by 40% by using 60°C (or perhaps 45°C depending on the reference) water for cooling. He posted a picture of it here. “The same idea will work with cooling channels cut directly into the silicon die in a 3D IC stack—in concept,” writes Leibson. I need some convincing here. It’s a matter of scale. Can this concept that works for a super computer really be adapted for smaller notebooks, iPads, and smart phones? Feedback is encouraged! Post your comments at the end of this blog!
Incidentally, last Thursday Leibson shared a Chip Estimate TV video from DAC 2012, in which Cadence’s Marc Greenberg explains the impact the adoption of Wide I/O TSVs will have on controller designs, You can access it here on EDA369 Insider.
Last week, Solid State Technology posted a retrospective on this year’ Confab, the franchise’s invitation-only event for the semiconductor industry that was held in Las Vegas in June. As I was one of those unable to attend, I perused the post, and was interested see the event has expanded its focus from front-end to include more back-end with a session titled Advanced Packaging and Progress in 3D Integration featuring an impressive line-up of key influencers in the 3D space from GlobalFoundries, Xilinx, nVidia, ASE And Amkor. Two posts cover the discussions that took place: Supply Chain or Supply Web for 3D Packaging? and. 3D and 2.5D Semiconductor Packaging Technologies.
Much of the Confab discussions appear to be a continuation of talks that began at the IMAPS Device Packaging Conference and during the Greg Bartlett’s keynote address and the packaging panel at ECTC . The message is the need for open collaboration and a creation of what Bill Chen (ASE) dubs “a virtual IDM” between fabless, foundry, and OSATS to develop a cost-effective solution that benefits all the players in the supply chain. As all of these events draw attendees from different corners of the industry, its good to hear a consistent message being shared, so that the high-level exectutives are hearing the same plea as the process engineers. That’s a step towards open collaboration right there. ~F.v.T