GSA’s Silicon Summit: Good News from the 3D Ecosystem Panel

I don’t get to attend all the 3D events that I would like to, and such was the case with this year’s GSA Silicon Summit, held Thursday, April 26, in San Jose. But I did get some insight from Rich Rice, Senior VP of Sales and Engineering, ASE, who was a panelist on the afternoon 3D Packaged IC Ecosystem panel discussion, and whom has also participated in a number of similar panel discussions over the past year. The panel was moderated by  Mark Brillhart, VP, Technology and Quality, Cisco Systems, Inc. and featured a line-up of panelists representing different segments of the 3D ecosystem, including Raman Achutharaman, Corporate V.P. Strategy & Marketing, Silicon Systems Group, Applied Materials, speaking out for equipment manufacturers; Liam Madden, Corporate VP, FPGA Development and Silicon Technology, Xilinx, from the end-user camp; David McCann, Senior Director, Packaging R&D, GLOBALFOUNDRIES, represented the foundry position; Stephen Pateras, Sr. Director, Marketing, Silicon Test Division, Mentor Graphics provided the design tool side, and Rich Rice, who offered an OSAT perspective.

Rice reported that similar to the other panel sessions this year, there was a clear message of forward movement for commercialization of 3D ICs, and all present shared a vision of an open platform ecosystem (TSMC wasn’t represented at this particular panel discussion) with variations on theme with regard to the middle of line (MOL) processes. It was Rice’s opinion that the companies with well-established bumping and RDL processes will be most likely to invest in the rest of backside processes. He emphasized, “If they have the capability already there, they’re more likely to make incremental capital investments.”  He went on, “The engineering know-how is also important.”

According to Rice, Pateras focused on design challenges of achieving coverage throughout different heterogeneous stacks, and how that translates to design and needs to be handled in the design domain. Design for Test is the key, and he reports that progress is being made in that area.

In the equipment side, Achutharaman’s key point was AMAT’s realization that there are two classes of customers to serve in the 3D space; the Fab and the OSAT. Basically, the OSAT doesn’t require the same capabilities that a Fab does.  The company intends to customize tools to accommodate both classes, and is putting effort into develop what they call “application refined” tools that are more cost efficient.  From an OSAT’s perspective, Rice was appreciative, noting that with current tools there’s “at least one more decimal point in the cost than we would like to see.”

While much of what Madden talked about reinforced previous Xilinx presentations about its Virtex FPGA silicon stack as the first product using a 2.5D/3D architecture, Rice said he offered some new information about reliability and redundancy that was a piece of particularly good news. It turns out that due to the having the same coefficient of thermal expansion (CTE), the interface and reliability between the logic chip and the interposer is “actually quite good” and it turns out that general concerns because of the additional layers of interconnect aren’t something we need to be concerned about after all. “We always thought that, being silicon on silicon, it would make sense that it would be more reliable,” said Rice. “But you can’t really know that until you start running product.”

McCann also addressed the topic of component reliability, saying that it all starts with a good design, taking into account designing redundancy into a chip so that missing one via or bump isn’t an issue. More good news came from him about thermal issues, which like reliability, has been a main concern. Here, it turns out that the TSV stacked chips’ close proximity to each other really drops the power and improves latency. Additionally, TSVs have proven to be very effective at moving heat, so they can be used as another “design knob”  for both power reduction and thermal management overall.

While we’re getting closer with ironing out the supply chain, there are a few challenges that remain when complex structures are involved. Who’s going to own what, and how will the different technologies be integrated? “In my opinion, it’s got to be a single owner and system integrator,” says Rice. “The owner is the one whose name is displayed on the top of the package.  It’s that company’s responsibility to make sure die are procured, and that the end product meets design and reliability specifications.” 

Capital spending is another challenge going forward, noted Rice. While some companies can leverage the existing infrastructure, there are MOL processes that require major capital investment.  Rice cited temporary bonding and debonding, and permanent bonding as mission critical. With regard to temporary bond and debond, there’s not a standard process in the factories today. And transition to thermo-compression bonding is different than the existing reflow process, and is thus another area to incur capital expense.  However, Rice noted on behalf of ASE and other OSATS that many of the companies are doing a lot of wafer-level processing, such as bumping and RDL, and adding additional WLP is “a challenge we can handle.”  Rice supported Achutharaman’s comment that more process and equipment standards are needed, however he also stated that this is a challenge because the packaging industry is not heavily standardized due to the variety of end-use products and silicon architectures. He also echoed the sentiment offered by Mark Brillhart, the moderator, who said that it’s really the packaging arena that will play a big role in 3D ICs going forward. Brillhart emphasized the need for a highly flexible supply chain, utilizing core competencies of the OSAT community.

As the session wrapped up, panelists considered the business model arena as related to building a supply chain model where everyone is profitable. On that topic, Achutharaman mentioned the importance of collaboration and synchronization, as well as development of standardized solutions, which are cost optimized while meeting performance requirements. Madden referred to Moore’s Law as being “not friendly”, and noted that the industry requires more system integration, while packaging  specifically needs to be less cost prohibitive. McCann mentioned that “customers are depending on us to collaborate, enabling customers to design.”  He also expressed the need for standardization and collaboration, as well as design for test (for yield).

After hearing about the panel session, I really wish I’d had been there. I hate to miss out on good discussions!  But at least I can always count on other 3D enthusiasts to update me.  Along those lines, I’ll be talking to Herb Reiter next. I’ll be sure to let you know what becomes of that.  ~ F.v.T.