Although I don’t often get to attend the GSA 3DI IC Workgroup meetings personally, I am on the mailing list and like to share the notes when they come my way. Harrison Beasley, technical working groups manager sent a brief review of the July 12 meeting that took place at eSilicon, San Jose as well as addressed some action items he’s been charged with. I did a little more digging (ok, I went online and read the meeting minutes, but we journalists like to make it sound more mysterious) so that those of you who didn’t attend can get a bigger picture. And if my version isn’t detailed enough, you can find the complete minutes here.
At the July 12th meeting, much of the discussion centered on 3D IC development business models and the associated assembly flows. For this reason, the October 24th meeting theme will be “3D IC Test”, with presentations from Gary Fleeman (Advantest) and CJ Clark (Intellitech).
The January 16th meeting theme will be “Business Models”, with presentations from Rich Rice (ASE) and Samta Bansal (Cadence) to continue our investigation.
To begin activity on working group deliverables, I (Beasley) took an action item to begin gathering and disseminating assembly flows from industry luminaries. Please see the attached slides provided by Ron Huemoeller (Amkor) as food for thought.
A presentation from Rich Rice (ASE), presented at the SEMICON West 2012 TechXpot panel session: “The 2.5D and 3D IC Packaging Landscape for 2015 and Beyond” has been posted here on the GSA 3DIC Working Group page.
Beasley will continue gathering information on 3D IC assembly flows for the working group to review. If you have material that you are willing to share, please send it to email@example.com.
The GSA 3D IC working group has determined that it can add value to the development community be defining and clarifying business models, with a consistent terminology. Your involvement in this effort is greatly appreciated.
Additional Nuggets from the Minutes
Ken Potts, Cadence said a10nm fab costs $10B, which is a tremendous investment for any company. He queried, how do we share the profit and loss, and is that the answer?
Warren Flack, Mentor Graphics says we need to reach consensus on what’s holding back 3D IC adoption: is it a lack of standards? Do we need better coordination?
In his presentations Professor Mike Bushnell, Rutgers kicked off a test discussion, recommending the group review the 3DIC test standards posted here on 3D Interconnect Wiki. Here’s why test problems for Through Silicon Via (TSV) are different from current silicon test problems? We’re dealing with via alignment, failures tend to be catastrophic, and typically there are no single TSV failures.
Warren Savage, CEO, IPextreme gave a presentation of the GSA CAP Lite Portal, which provides a centralized place where suppliers (IP, EDA, Services, Venture) could be connected to entrepreneurs. Here’s a presentation that explains the full concept. He suggested it could be a useful tool for 3D IC business models.
Defining terms seems to be of great concern. Even what is meant by “business model” needs to be defined. The GSA 3D IC Working Group sees itself as a “business intelligence function” and has assigned itself with building “a glossary of terms” to provide a common language for the arena. Considering all the different definitions floating around out there that seems like a GREAT idea to me.