Earlier this week, Mitsubishi Heavy Industries, Ltd. announced it had “developed the world’s first fully automated 12-inch (300 millimeters) wafer bonding machine, capable of producing 3-dimensionally integrated LSI (large-scale integration) circuits at room temperature.” This tool is targeted to the MEMS, 3D LSI’s, and the RF market.
I was skeptical of the words “world’s first” when I know that both EV Group and SUSS MicroTec have fully automated wafer bonders that can perform room temperature, wafer-to-wafer bonds, and are well established in the MEMS, RF and 3D IC market. I decided to find out what was different about this tool that would allow them to claim to be first in the industry. Here’s what I found out from Hideo Ikuno, Media Relation Manager for MHI.
According to Ikuno, while EVG Group and SUSS MicroTec tools perform “plasma activation bonding”, which requires heating at 200 ℃ at the anneal step to form the permanent bond, MHI’s process, called Surface Activated Bonding (SAB) was developed in Japan and takes place completely room temperature. He compared the processes as follows:
Plasma Activation Bonding adopted by EVG/SUSS:
1. Uses oxygen plasma to create a hydrophilic surface.
2. Water treatment on the surface.
3. Forms a “temporary bond” at room temperature with hydrogen.
4. Annealing at 200℃ for 2-3 hours to form the permanent bond.
MHI’s process:
1. Remove oxide layer on surface by Neutral Atom bombardment in vacuum.
2. The activated surface (dangling bond) appears on the surface .
3. Two wafers come in contact to form a permanent covalent bond with reportedly the same bond strength as base metal . The entire process takes place at room temperature.
SAB was first developed for MEMS, and later expanded to include RF devices. Until this tool was introduced, the largest wafer size that could be accommodated was 200mm. For 3D ICs, the company claims the room temperature process will allow for stacking of TSV wafers with high alignment accuracy and no thermal stress. It also is said to allow for increased productivity because the heating/cooling cycle is eliminated. Finally, the process can be applied to various materials such as silicon, compound semiconductors, crystal oxide, and metals (Au, Cu, Al, etc.)
The first tool has been delivered to the National Institute of Advanced Industrial Science and Technology (AIST), where it will be used in development to enhance capacity and performance of 3D LSI circuits. It will be interesting to see what this tool can offer with regards affecting the cost of wafer-to-wafer stacking for memory and microprocessors.
