The SEMICON West 2010 show at Moscone Center in San Francisco, from July 13-15, will present a full program of exhibitions, presentations, meetings, and workshops focused on 3D interconnects (3D IC) for integrated circuits. Show exhibitors in the 3D IC segment, including Applied Materials, Tokyo Electron, Lam Research, and SUSS MicroTec, represent the industry’s largest gathering of 3D IC companies at one event.

The 3D IC programs will showcase leading-edge approaches to this 3D chip and package technology, which enables smaller, lighter, and faster multi-chip packages. Adopting this technology throughout the industry will have a significant impact on the entire semiconductor supply chain, from chip concept and design into the manufacturing fab and then through final assembly and test.

  • The 3D IC events begin with the Qualcomm 3DIC Keynote and a through-silicon via (TSV) Technical Session at the Advanced Semiconductor Manufacturing Conference (ASMC), which runs from July 11 to July 13.
  • The market opportunities for 3D IC will be highlighted in the SEMI/Gartner Market Symposium, to be held on July 12.
  • The SEMICON West 2010 TechXPOT Programs held on July 13 and 14 will discuss TSV/3DIC Current Issues in the “Bridging the Packaging Gap” session, and the “Swimming the Packaging Channel” session will address TSV/3DIC: Trends and Challenges Today.
  • In addition, the TechSITE Program on July 13th from 2:00pm–4:30pm will feature a presentation on “3D IC Co-Design Challenges: How to Speed 3D IC Deployment”.

SEMICON West 2010 also has several workshops held by SEMI and its SEMICON West partner organizations. The SEMI/ SEMATECH Workshop on “3D Interconnect Challenges and Standards Needs” will take place on July 13, and the SEMATECH “Workshop on 3D Interconnect Metrology” will happen on July 14.

Also on July 14 are the “ITRS Roadmap Public Meeting” and the International Microelectronics and Packaging Society (IMAPS) “Workshop on Advanced Interconnect Technologies”.

In partnership with IMAPS, SEMICON West 2010 will also include a special exhibit pavilion area for showcasing 3D IC products and technologies. Located in Moscone North Hall, the IMAPS – SEMI 3D IC Pavilion will include suppliers from test, packaging, wafer processing, and design.

“The leading edge of semiconductor packaging today – and for the foreseeable future – is 3D IC,” said Tom Morrow, vice president of Global Expositions and Marketing at SEMI. “All parties in the supply chain are looking for cost-effective solutions and for partners who can help bridge theory and practice while overcoming the challenges of bringing this technology into high-volume manufacturing. SEMI is pleased to have the support and cooperation of IMAPS, SEMATECH, and all of our event partners as we help the industry focus on the challenges and solutions that will bring this technology into widespread use and profitability.”

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