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Two years ago, IMAPS tested the waters for a new conference focused entirely on system-in-packaging (SiP) technologies. They had also recently acquired the 3D Architectures for Semiconductor Integration and Packaging Conference (3DASIP), originally produced by RTI Tech Venture Forum, which took place annually in December in San Francisco. The IMAPS...
The cynic inside often thinks “All hat, no cattle” about the newest new, new thing (right, Michael Lewis?). But if you were to consult the Gartner Hype Cycle listings from 2008 as I just did you would find, perhaps to your surprise, that Cloud Computing, 3-D Printing, Solid-State Drives, and...
The Winter Games are over and the athletes returned home, and the SEMICON Korea 2018 teams from February have their sights on SEMICON China this month after all that snow-in-Seoul settled, but I still have a few more comments about the Electropackage System and Interconnect Product technical session SEMI organized...
Semiconductor device fabrication and packaging is rife with acronyms, and by my estimate, the Top 3 trafficked by speakers at the recent IMAPS Device Packaging Conference were the acronyms FOWLP, FOPLP, and MEMS. That would be fan-out wafer level packaging, fan-out panel level packaging, and microelectromechanical systems, respectively. It wasn’t...
“It is better to be first than it is to be better.” (Ries and Trout, in The 22 Immutable Laws of Marketing.) Or is it “Fast Followers Not First Movers Are The Real Winners?” Fan-Out Wafer Level Packaging has built up such a head of steam this year (see “iPhone...
