What does it take to stand up 30,000 sq.ft. of chips‑last fan‑out wafer‑level packaging capacity at scale?
This photo shows what we’re calling the “ballroom”, soon to be completely stripped down and rebuilt as a ~30,000 sq.ft. chips‑last fan‑out wafer‑level packaging assembly line.
The space will be transformed into a Class 1000 cleanroom, equipped with state‑of‑the‑art tools (with the assembly line equipment already ordered) and enabled by IBM’s world‑class Smart Factory systems.
We expect to qualify the line in Q3 2027, in parallel with bringing in‑house wafer bumping online.
Come by booth #101 next week at IMAPS DPC if you’d like to learn more about our production ramp plans.
