Don’t miss a full morning of expert presentations about 3D-IC and Interposer design tools and methodologies!

Since 2004, every December RTI International has organized  a 3D technology focused conference in Burlingame, near the San Francisco Airport. Supply side industry experts presented the progress they had made in developing new manufacturing and metrology equipment, advancements in material characteristics, TSV manufacturing, thin wafer handling, assembly and test of multiple dies in an IC package. IC- and system designers presented the experience they had gained with evaluation units and presented a long list of capabilities still missing, to make interposer and 3D-IC design and manufacturing more user-friendly and much more cost-effective. This year’s conference will offer a lot of additional value for IC and System designers.

Why? During 2014 the big 3 memory vendors – Micron, Samsung and SK Hynix – have not only provided many evaluation samples to customers, but have ramped volume production of High-Bandwidth-Memory (HBM) and Hybrid Memory Cube (HMC). These, I call memory sub-systems, provide several 100MB of bandwidths and cut power dissipation to a fraction of what DDR modules consume. The next generation graphics designs, compute servers and networking equipment to be introduced in 2015 and ‘16 will utilize these memory cubes, combined with logic chips on interposers. These applications will drive production volumes and cost-reduction efforts for interposers and 3D-ICs and make these technologies compelling for more cost-sensitive applications.

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Here is another trend I have observed in 2014:
As a number of larger companies have completed one or more evaluation design, they are now moving on to prototyping of interposer and 3D-IC designs, destined for actual deployment in their next generation systems. To walk the fine line between costly over-design and unreliable under-design, they demand better EDA design tools and more accurate models of material characteristics and manufacturing capabilities. Ansys/Apache, Cadence and Mentor as well as several smaller EDA vendors are utilizing these opportunities to expand their interposer and 3D design tools and modeling capabilities and mature them, based on very valuable customer feedback.

After briefly analyzing these two major trends, let’s talk about how RTI responded to these major market developments. Unlike in the previous 10 years, when only a few presentations about interposer and 3D design tools were scheduled, this year’s 3D ASIP conference will increase the number of design-centric presentations significantly, even dedicate half a day to EDA and design topics:

Please join us on Wednesday morning, December 10, at 8.30 am, for four hours of EDA and design-centric presentations. EDA experts from Ansys, Cadence, eSystem Design and Mentor will present what their teams have developed to enable user-friendly interposer and 3D-IC design. Globalfoundries will outline their support for these technologies, Rambus will share the experience gained when developing interposer IP and Qualcomm will talk about the importance of silicon-package CO-design. Last but not least, Jerry Frenkil, a well-known low power design expert and Si2 low-power consultant, will outline how to minimize power dissipation and cooling challenges in interposer and 3D-IC designs.

In addition to four hours of presentations and Q & A, you’ll also get a soft copy of the 2014 edition of the Design Guide for interposers and 3D-ICs. Its 66 pages, with many web pointers, include a detailed introduction to the 3D EcoSystem as well as lots of information about the 3D tools Ansys/Apache, Atrenta, Cadence, Docea Power, eSystem Design, Mentor Graphics, MicoMagic and Zuken offer. Other important 3D EcoSystem players who contributed information to this Design Guide are: 3D InCites, eSilicon, GSA, IMEC, Kilopass, Savansys, SEMI, Si2 and TechSearch International. In the appendix you’ll find web pointers to long lists of 3D-IC specific books, to 3D centric industry conferences and to recent news about interposer and 3D-IC announcements.

If your schedule allows, please join us on Wednesday morning, December 10, near SFO airport for the (3D ASIP). Register here for this $499 EDA-centric symposium, which includes the conference proceedings and Design Guide.  For only $ 250 more you can also attend the 3D process technology session on Wednesday afternoon and get the Handbook of 3D Integration, Volume 3, as a bonus.

When you look at the entire program for this three-day conference (We, Th, Fr), you’ll find other EDA-focused keynotes and presentations and a Pathfinding Panel. EDA standards, Internet of Things (IoT), memory advances, process technology, interposer and packaging topics and a look at the future are also on the agenda.
I look forward to meeting you – especially if you are an IC or System designer – next Wednesday at the EDA session I have helped to organize and hope you’ll find many other topics useful for you during these three days. ~ Herb

Herb Reiter

After more than 20 years in technical and business roles at semiconductor and EDA companies,…

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