Like many years before, I had the opportunity to attend the annual TSMC Open Innovation Platform Ecosystem Forum in San Jose’s Convention Center, held this year on September 30, 2014.
TSMC always has a lot of progress to report from year to year. Last week’s event was no exception and demonstrated that this large corporation has the finger on the pulse of our industry. In my eyes, the most impressive examples for TSMC’s responsiveness and vision was Dr. Cliff Hou’s announcements of their 16nm and 10nm process capabilities to serve the rapid expansion of data centers, and the disclosure of their ultra low-power (ULP) processes for Internet of Things (IoT) devices.
Having experienced the power and benefits of alliances for many years, I found Rick Cassidy’s and Dr. Mark Liu’s emphasis on collaboration to be a very good strategy to further grow TSMC’s market share. By the way, collaboration was also a major topic at the recent Intel Developer Forum in San Francisco. Hearing the largest foundry and the largest IDM emphasize the need for collaboration and partnerships in our industry gives me hope that the complex and multi-disciplined requirements of 2.5/3D IC technology can be met jointly, and its technical benefits and system-cost advantages will become widely available.
Let’s stay for one more paragraph with my favorite technology topic: 2.5/3D ICs. TSMC hinted that, in addition to the powerful CoWoS and the lower-cost InFo technologies, they’ll introduce an even lower cost wafer-level packaging (WLP) alternative. Adding to the proven multi-die FPGAs TSMC manufactures for Xilinx, and the recently announced GPU and HBM design with Nvidia, TSMC presented their latest success in packing multiple dice into one package. In cooperation with HiSilicon, Huawei’s semiconductor group, and ARM, they combined two 32-bit Cortex A57s in 16nm, with a 28nm I/O chip and a number of passives in one package. We’ll soon hear more about this powerful network processor and the impressive bandwidth and latency specifications it can offer.
At this point you may ask: What specifically will TSMC do for me to sell some of the billions of low-power IoT devices? Dr. Cliff Hou announced that TSMC is developing ULP version of their 55, 40 and 28nm processes, and works closely with several EDA partners to develop ultra low-power design flows. If your IoT design will need RF and/or Flash, TSMC will have it ready for you mid 2015. Please check with your TSMC contact for further details; Cliff announced so many new capabilities, I had a hard time capturing every detail he presented.
A few more words about Mike Muller’s keynote at the Symposium: Traditional for ARM, he stated again what I heard from him and Sir Robin Saxby back in 1990: “It’s all about Power (dissipation)”. What I heard for the first time, was that CMOS devices can operate down to 0.2 Volts. Considering that active power dissipation equals C V2 f, this means that the active power is only 4% of what the circuit would need at 1 Volt. Mike also emphasized what many IoT experts have told me before: Data- and program security is a major concern in the minds of IoT designers and users. My friends at Kilopass confirm this. Their highly secure antifuse technology addresses these critical points effectively and is very popular in IoT circles.
During the afternoon sessions many of TSMC’s 100+ ecosystem partners presented their strengths and outlined their work with TSMC’s Design Enablement Team.
All of these cooperation examples are music to the ears of an Austrian Alliance Manager. ~ Herb
Before end of this year, what other conferences will talk a lot about packing multiple dice into one package to reduce power, formfactor and time-to-market, while increasing speed and bandwidth? Just as a reminder and service for you, here is a list of pointers:
- International Symposium on Microelectronics (IMAPS) 13-16 October 2014, San Diego, CA
- memcon Oct 15, Santa Clara, CA
- MEPTEC Symposium, Oct 23, San Jose, CA
- 3D TEST Workshop, Oct 23 & 24, Seattle, WA
- Annual Global Interposer Technology (GIT) Workshop GeorgiaTech 5-7 Nov 2014, Atlanta, GA
- International Wafer-Level Packaging Conference (IWLPC) 11-13 Nov 2014, San Jose CA
- 3D Architectures for Semiconductor Integration & Packaging (3D ASIP) 10-12 Dec 2014, Burlingame, CA