A memory stack on logic 3D TSS stack was considered for comparative study of warpage response to two different
process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling
software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.
In this work D2D and P2D stacking approaches are evaluated by comparison of chip/substrate warpage at various
attach and post attach room temperature stages of assembly process flow. A notable competing flow is the W2D process, which is out of the scope of this work and will be addressed in a future work.
This paper was originally presented at ECTC 2013, in Las Vegas, Nevada, and was submitted to 3D InCites by the author as supporting data for Cielution’s submission for the 2013 3D InCites Award for design tools.