SUSS MicroTec has appointed Dr Rainer Knippelmeyer as VP R&D and CTO. In this function Rainer Knippelmeyer will oversee research and development and innovation management for all products. His main focus will be on the creation of a cross-product technology roadmap within the SUSS MicroTec group. Rainer Knippelmeyer has many years of experience in research and development from his employment ... »
You know how sometimes you feel like you know a person you haven’t actually met because you read something they wrote or sat through a presentation? And then when you finally meet face to face, it’s like meeting an old friend, “Oh you’re so-and-so!! I feel like I already KNOW you!” That’s how it was when Karen Lightman, of MEMS Industry Group (MIG), and I met at SEMICON West; first a... »
In an ongoing effort to drive 3D IC integration, SEMATECH’s 3D Interconnect program has completed its 300mm 3D IC pilot line, operating at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex. Dedicated to via-mid 3D applications, SEMATECH’s development and exploratory platform includes all processes and test vehicles necessary to demonstrate the viability of the »
A critical challenge for fabricating 3D products is the integration of the dies with through-silicon vias (TSVs) into functioning and reliable 3D stacks. As a way to assess and overcome the risks, imec has created the SmartSamples platform. SmartSamples allow validating 3D stacks before the actual product design, avoiding costly re-spins and additional expenses. They are IC emulators, prototype 3D »
My recent visit to EV Group at its headquarters in Schärding, Austria, included some time spent with M. Jürgen Wolf, who, as part of his management and coordination of Fraunhofer IZM-ASSID (All System Silicon Integration Dresden) is the program & project manager for 3D Wafer Level System Integration (WLSI) and wafer-level packaging (WLP). There’s been a lot of activity going on with Frau... »
SEMATECH, the Semiconductor Industry Association (SIA), and Semiconductor Research Corporation (SRC) announced today they have established a new 3D Enablement program to drive cohesive industry standardization efforts and technical specifications for heterogeneous 3D integration. Administered by SEMATECH’s 3D Interconnect program, based at the College of Nanoscale Science and Engineering (CNSE... »
Today’s side trip to the GSA’s 3D EDA Interest Group’s bimonthly meeting (sandwiched between IEDM 2011 and RTI’s 3D Systems Integration Conference) proved to be worth the trip for several reasons, but particularly for the “behind the curtain” glimpse at Xilinx’s stacked silicon interconnect technology that was introduced to the market several weeks ago. Arif Rahman, principal engi... »
SPP Process Technology Systems (SPTS) announced the opening of its new facility in San Jose, CA, serving as the home for the company’s Thermal Products Division, and sales and support headquarters for North America. The Thermal Products Division was relocated from Scotts Valley, California. In October 2009, Sumitomo Precision Products (SPP) acquired assets of Aviza Technology and subsequently i... »
I have to say that this was THE quote of last week, uttered by MEMS Industry Group’s managing director, Karen Lightman, neatly summing up the main reason why the MEMS Executive Congress, held this year from November 3-5 at the sumptuous Montelucia Resort and Spa in Scottsdale, Arizona, drew everyone who’s anyone in the MEMS community. This event was different than most of the ones I attend f... »
Sometimes I like to mix it up a bit. So last night I was the invited guest speaker at the BiTS workshop, an event focused on the latest information about burn-in and test socketing, as well as semiconductor test issues. I was asked to share what I know about 3D packaging, and particularly 3D TSV test issues. I hope I did justice to our collective cause! »
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