The leading event for Chiplet and Heterogeneous Integration Packaging (CHIP) technology addressing the challenges and opportunities for enabling broader adoption of chiplet architectures
The IMAPS CHIPcon conference will be held July 7-10, 2025, at the Marriott in downtown San Jose, California. This event will focus exclusively on the innovative device integration approaches, technology developments, solutions, and business trends enabling the continued advancement in semiconductor device (system) performance. CHIPcon 2025 will offer cutting-edge presentations from scientists, technologists and business leaders across the globe with expertise in high performance computing, networking, automotive, cellular, and mobile market (consumer) segments.
“The adoption of chiplet-based, heterogeneously integrated device architectures has clearly reached critical mass. Initially for high performance compute and AI accelerators and now expanding to other devices and applications as the benefits of this approach are recognized,“ said Eelco Bergman, CHIPcon Co-General Chair. “In organizing CHIPcon 2025, our objective was to bring together leading industry experts to address the challenges and opportunities for enabling broad based adoption of chiplet architectures and establishing a viable design and manufacturing ecosystem. We’re confident that we’ve achieved our goal and look forward to welcoming our industry colleagues to an another outstanding IMAPS event.”
CHIPcon 2025 will explore the current state of the art in design, simulation, packaging, test, process, and material technologies supporting the integration and delivery of a complete semiconductor system or subsystem solution. Attendees will be exposed to thought-provoking advanced device and package structures with high functioning system performance, mechanical reliability, thermal management and high yield manufacturability.
Ou Li, Co-General Chair states, “We’re delighted to welcome attendees to CHIPcon 2025, returning to San Jose this year! The event is moving to a new venue that offers ample space and amenities to support our technical program and exhibits. This year’s program features professional development courses, keynotes from leading market and industry experts, two insightful panel discussions, and six technical sessions. Topics will include chiplet integration and design flows, chiplet ecosystem development, device integration and packaging technology, test and metrology, emerging materials and process tools, and—new this year—optical interconnects and silicon photonics.”
The keynote lineup includes: Ashkan Seyedi (NVIDIA) – “AI Inference Scaling Through Advanced Packaging Interconnect”; Mukund Chavan (Rivian) – “Modern Autonomy Compute Challenges & Opportunities for Disaggregation”; and Mario Morales (IDC) – “Semiconductor Outlook: Intersection of Company Leadership, Policy, and Innovation”. The panel sessions will focus on “Transforming Chiplet Technology to Large Scale Manufacturing – Challenges and Opportunities” and “Chiplet Ecosystem, The Road to Democratizing Chipset Adoption”.
