2018 3D InCites Awards Nominees

2018 3D InCites Awards Nominees

NOMINATIONS HAVE BEEN EXTENDED TO WEDNESDAY,  FEBRUARY 14, 2018. VOTING OPENS MONDAY, FEB 19, 2018.

The nominees for the 2018 3D InCites Awards are listed below by category. Winners will be chosen by industry peers, through an online voting process. We are accepting nominations through February 15. Online voting opens Monday, Feb 19, 2018, and closes Thursday, March 1,  2018.

Device Manufacturer of the Year

Amkor Technology

Amkor Technology Portugal (ATEP), formerly NANIUM is a world-class provider of semiconductor packaging, assembly and test, engineering and manufacturing services. ATEP offers in-house capabilities for the entire development chain, from design to multiple wafer level packaging (WLP) technologies, and the flexibility to tailor and test solutions that respond to the most demanding customer requirements. The company is now a leader in 300 mm WLP, both Fan-in Wafer Level Chip-Scale Package (WLCSP) and Wafer Level Fan-out (WLFO), based on embedded Wafer Level Ball Grid Array (eWLB) technology.

Samsung

As the industry moves Beyond Moore, there has been much efforts for the next-generation of packaging, among which Fan-out packaging technology is getting significant attention with its high-degree heterogeneous integration capability and small form factor. With steps on the mass production stage of fan-out package, Panel level packaging is emerging as the most cost-effective technology featuring a large and efficient working area for a varied unit size and array. Samsung has been preparing Panel Level Packaging for several years with addressing some of significant technical challenges such as handling large size panels, proving much high level of yield, and RDL formation of fine pitch pattern for specific applications, and is now reporting on development results to expand the applications of Panel level package as well as fundamental achievements for manufacturing PLP, with an emphassis upon fine line/space patterning.

Rogue Valley Microdevices

Founded in 2003 and based in Medford, Oregon, Rogue Valley Microdevices maintains a 200mm MEMS devices foundry, supporting its customers from early R&D through pilot production. As a full-service precision MEMS foundry, the company combines state-of-the-art process modules with the engineering expertise to go seamlessly from custom design to manufacturing. Specializing in MEMS and biomedical device manufacturing, Rogue Valley Microdevices offers a flexible equipment set and smaller batch sizes, playing a critical role in the commercial MEMS manufacturing ecosystem.

What Makes the Company Different?
Rogue Valley Microdevices understands the importance of close customer relationships. The company engages in open dialog with customers, prioritizing their needs and goals. Rogue Valley Microdevices will also support customers’ existing supply chains.

Because MEMS manufacturing processes are unique to each customer, Rogue Valley Microdevices shares engineering-level data with its customers, freeing them to bring up a process at Rogue Valley Microdevices that they will later use for high-volume production at a larger fab.

What’s more, Rogue Valley is truly a MEMS fab. It has gold and platinum as part of its normal processing — without the many restrictions that most other fabs place on their use. Rogue Valley Microdevices is experienced with nanoscale advanced materials, including graphene.

Rogue Valley also maintains the broadest and most comprehensive set of wafer services commercially available — with over 50 unique dielectric and conductive thin films and all services performed in the company’s own class 100 cleanroom.


Device of the Year

M-Series™, Deca Technologies

Wafer level fan-out packaging has been recognized as a technology with attributes that address many of the challenges the industry faces with more conventional approaches. M-Series addresses some of the key limitations the incumbent approaches faced courtesy of the adaptive processing combined with planar front side molding. The investment of over $110m in Deca by two of the giants of the industry is testimony to this technology.

Apple A11 Processor

The A11 is manufactured by TSMC using a 10 nm FinFET process and contains 4.3 billion transistors on a die 87.66 mm2 in size, 30% smaller than the A10. It is manufactured using TSMC's InFO PoP for IPhone 8, 8+, and X.

Menlo Micro MM3100

The MM3100 has come on the scene in 2018! This amazingly small, yet powerful device is starting to bring transformative improvements in size, weight, power and performance to various end markets, most notably software defined radios and tunable RF front-ends. This low-profile surface mount package (6mm x 6mm x 1.4mm) packs an embedded controller and (6) high-power, lossless mechanical switches, manufactured with Menlo's proprietary metal-on-glass Digital-Micro-Switch technology. An industry-first in packaging and integration, the MM3100 can handle upwards of 75W without generating excessive heat, and allows customers to replace large numbers of components such as PIN diodes, drivers, and even electromechanical relays, enabling a new generation of lightweight, high-power tunable radios.

Nanomedical Diagnostics

Through a partnership with precision MEMS foundry Rogue Valley Microdevices, Biotech company Nanomedical Diagnostics has introduced the first mass-produced graphene biosensor available, Agile R100.

What’s was the challenge?
• Drug discovery today is a laborious and costly process. To evaluate new drugs, most researchers test candidate compounds using expensive and complex laboratory equipment. Special training is a requirement, and testing can take days or weeks.
What do they offer?
• Nanomedical Diagnostics offers an alternative technology to the expensive and resource-intensive surface plasmon resonance (SPR) and bio-layer interferometry (BLI) tools generally used today. The company’s novel sensing technique — which features the world’s first commercially available graphene biosensor — allows pharmaceutical and biotherapeutics companies to characterize biomolecules quickly and easily, transforming the field of drug discovery.
Why graphene?
Graphene is one of the world’s most versatile material capable of revolutionizing biomedical applications due to its excellent electrical conductivity, high surface area and unique bio-compatibility. However, it is notoriously difficult with which to work – as manufacturing with graphene is largely undocumented.
How did they do it?
They partnered with Rogue Valley Microdevices. After doing some pre-processing, Rogue Valley Microdevices ships the wafers to Nanomedical Diagnostics. Using the highest-quality graphene, Nanomedical Diagnostics handles graphene growth and deposition in a clean and non-destructive way without the use of harsh chemicals.
Rogue Valley Microdevices completes the MEMS device fabrication process, which produces several hundred chips from each finished wafer. The end-result is the first commercially available graphene biosensor.

AerNos

Through a partnership with precision MEMS foundry Rogue Valley Microdevices, AerNos offers an ultra-miniaturized, affordable gas sensor technology that can monitor air quality on an individual level.

What’s was the challenge?
Monitoring the air we breathe is an enormous challenge because air quality varies dramatically, depending on location. That is why having the ability to measure air quality on an individual basis is so important. Armed with information on airborne toxins in our surroundings, we can act to reduce exposure by changing our location. We can also employ automated air purification systems, automated ventilation systems, and connected IoT devices that reduce emissions when air quality is poor.

What do they offer?
AerNos’s MEMS-based 3 mm x 3 mm sensor chip uses hybrid nanostructures to simultaneously detect specific gases in indoor and outdoor environments. In addition to their small size, low power and affordability, AerNos gas sensors can detect multiple gases simultaneously -- a major improvement over competitors that can detect just one-two gases.

How did they do it?
Rogue Valley Microdevices fulfilled AerNos’ requirements: selectivity, sensitivity, low power consumption, and stability of its technology, all while using nanomaterials, including carbon nanotubes — which are highly sensitive to the environment. Rogue Valley Microdevices used nanomaterial doping processes to create nanostructures where shape, size, density and location of nanomaterials are fabricated with precision. The AerNos gas sensor is the result of this manufacturing partnership.

OmniVision Technologies' OS05A20 Image Sensor with Nyxel™ Technology

The OS05A20 is OmniVision's first image sensor with the new Nyxel™ technology for near-infrared (NIR) sensing, which leverages novel silicon semiconductor architectures and processes to tackle the challenges plaguing NIR image sensors. This 5-megapixel color image sensor leverages both the PureCel® pixel architecture and Nyxel technology to capture bright, crisp videos and images, day and night. The OS05A20 achieves a significant improvement in quantum efficiency when compared with OmniVision's earlier-generation sensors. As such, the OS05A20 can "see" better and farther under low- and no-light conditions, making it an ideal imaging solution for professional surveillance systems.


EDA Provider of the Year

Mentor, A Siemens Business

On behalf of Mentor, A Siemens Business, at a number of 3D-IC focused conferences in 2017, Juan Rey, VP, conveyed not only its capabilities in supporting 2.5/3D-ICs, but also explained why and where EDA tools and design methodologies are important for developing cost-effective solutions and get them right the first time.

Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today’s ICs, advanced IC packages, and PCBs. Cadence IC packaging and cross-domain co-design technologies are the de facto standards in system-level co-design and advanced IC packaging, delivering automation and accuracy to expedite the design process. In 2017, Cadence announced new capabilities to complete an integrated design flow developed earlier in collaboration with TSMC for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Cadence’s integrated design enablement solution includes implementation, signoff and electro-thermal analysis tools that enable concurrent multi-chip optimization for designs incorporating InFO technology. Cadence’s new Virtuoso® System Design Platform integrates the Virtuoso, Allegro®, and Sigrity™ platforms, providing the industry’s first complete flow focused on heterogeneous integration. Cadence customers can now perform package-level LVS—an industry first—and IC signoff, including system-level layout parasitic effects. Cadence and ASE recently announced a System-in-Package EDA solution that addresses the challenges of designing and verifying Fan-Out Chip-on-substrate (FoCos) multi-die packages. The solution consists of the SiP-id™ design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow.


Engineer of the Year

Herb Reiter

According to Herb Reiter, our industry enjoyed the benefits of continued feature size shrinking for 5 decades. However, following Moore's Law to 10 nm features and below, is no longer economical for most IC applications. New IC technologies are needed to economically and timely serve many markets. Multi-die ICs (a.k.a. 2.5D & 3D-ICs) are a promising alternative versus following Moore's Law of continued shrinking. They have already proven their value in a number of applications. A fewmulti-die IC designs are scheduled to ramp into high-volume production in 2016 and will help maturing the multi-die EcoSystem, lower cost and time to profit.
And Herb is leading the charge, as both a technical consultant, and as an industry evangelist.

Gerard John

As the leading “Test Technologist” Gerard John functions as the “one voice” for Amkor Test- covering a wide range of products – such as commercial MEMS devices, 60GHz (collision avoidance) , high speed photonics and Wireless Cellular Communications products, and System Level Test, with a primary focus of test innovation and providing solutions that lowers cost of test. Gerard's speaking engagements have been many, and prominent, featuring the great engineering work he and his colleagues have been putting on the record, to the benefit of our industry and its customers.

Norman Chang, VP at ANSYS/Apache

Norman Chang significantly contributed to ANSYS' Power and Signal Integrity tools development efforts and is the "GO TO" expert when a customer has complex questions about his/her specific use case.

Gill Fountain

Gill Fountain, received his BS in Electrical Engineering at North Carolina State University 1980 and his MSEE in 1982 studying Deep Level Transient Spectroscopy. As a process engineer at Research Triangle Institute from 1982-2000 he focused on plasma processes and primarily worked in compound semiconductors. As a cofounder of Ziptronix from 2000-2015, he was known as the engineer who could bring the magic to the lab. If you visit the original Ziptronix Lab, you are sure to find more than 10 pieces of equipment designed and built by Gill. The Gillco brand equipment is known for its robust, repeatable performance. Since 2015, Gill has been our Zip guru at Xperi and we continue to learn from and with him as we extend the DBI technology to new market applications. Gill embodies the definition of a humble process engineer that you want on your team. He uses his extensive education and working experience to seek a fundamental understanding that drives the process optimization. His success as an engineer is a tribute to his creative acumen mixed with a clever practical approach.
One of his recent significant contribution at Xperi was expanding the chemical mechanical polishing process window for Cu damascene from relatively fine features. His team developed a process that delivers uniform, smooth Cu/Ta/Oxide surfaces with a controlled Cu recess with very small variance across wafer sizes. He has been an integral part of Xperi's technical team and his work allows the electronics industry to apply direct bond interconnect (DBI) for high volume die to wafer applications.

Seth Molenhour, Brewer Science

Seth Molenhour has been instrumental in developing numerous industrial solutions within our wafer-level packaging business unit, in addition to implementing continuous improvement processes as an Associate Applications Engineer with Brewer Science. Molenhour not only works hand in hand with our internal R&D, applications, and manufacturing groups to improve our processes, but he is also a key contact with customers and equipment partners for developing critical demonstrations and processes that ensure the completion of state-of-the-art solutions in a timely and effective manner. He is an essential part of Brewer Science's success as a materials and solutions provider within the advanced packaging industry.


Equipment Supplier of the Year

KOBUS

KOBUS, thin film deposition equipment supplier, is offering a unique solution that combines the best of both worlds: PEALD and PECVD. Unique and patented, our offer leverage classical thick film and conformality paradigm in many fields: TSV for 3D interconnects, µ-displays, MEMS & sensors, 3D LED, photonic on IC and more.

FRT GmbH

FRT GmbH – FRT MicroProf® FRT manufactures highly accurate tools for surface metrology. Our products combine multi-sensor technology and hybrid metrology in one measuring system. With the third generation of multi-sensor surface measuring devices, FRT is at the forefront of the market. The MicroProf® carries out a wide range of measurement tasks for 3D IC, Advanced Packaging and MEMS applications quickly, efficiently and intuitively. MicroProf®'s proven optical multi-sensor technology measures the topography,  and the total thickness or the film thickness of your samples without contact. Various optical measurement methods, which are only available as individual solutions elsewhere, have been combined into a universal, space-saving device. Depending on your requirements, the MicroProf® allows you to perform quick overview measurements of the entire sample, as well as high-resolution detail measurements down to the sub-nm range. This is made possible by the individual combinations of the sensors. Maintain flexibility for your future measurements and retrofit sensors easily and quickly, saving space, time and costs.

Intevac, Inc.

Intevac developed barrier/seed layer processes for fan-out wafer level packaging and fan-out panel level packaging redistribution layer formation on its carrier-based linear transport PVD system, MATRIX PVD, using a process sequence of degas – pre-clean – Ti PVD – Cu PVD. Each of the process modules on MATRIX is optimized to accommodate high throughputs and short takt times in order to produce Cost of Ownership advantages in fan-out packaging over the per-wafer or per-panel costs of the PVD cluster tools that are the current Process of Record in the advanced packaging industry. And by using dedicated wafer, or dedicated panel, carriers in the MATRIX system, it’s easy to change from running multiple 300mm fan-out wafers to running large panels for fan-out panel level packaging; the switch is made solely by changing the carrier itself, without making any in-vacuum adjustments for either the wafers or the panels.

SPTS Technologies Ltd

SPTS Technologies provides plasma etch and deposition equipment which has enabled many of the recent advances in 2.5/3D integration. Working on leading edge technologies with renowned research institutes, and helping to implement the best processes at leading device manufacturers, foundries and OSATs, SPTS has been at the forefront of developing a number of key wafer processing techniques and transferring these into full scale production.

Notable contributions include high productivity PVD of UBM/RDL for FOWLP with multi-wafer degas to double wafer throughput and reduce Rc, and a new pre-clean etch module to reduce contaminants and increase MTBC. Our expertise in deep silicon etching has been recognized within the MEMS arena for decades since bringing the first commercial DRIE system to market in 1995. This DRIE technology has been successfully transferred to 3D-IC packaging for through silicon via (TSV) etching, and into plasma dicing of standard and taped wafers up to 300mm. Other processes include low temperature PECVD for dielectric deposition onto standard, bonded or fan-out wafers, and HF/XeF2 release etch for MEMS release or wafer level packaging applications. Recent acquisitions have expanded our portfolio to include Molecular Vapor Deposition (MVD®) which is used for anti-stiction films for MEMS and anti-oxidation & -corrosion layers for packaging applications. Finally, from the PCB division, we can also offer inkjet products for 3D printing of underfill dams and isolation layers, and laser systems for through-mold via formation.

Nordson

Contaminants produced during semiconductor manufacturing often inhibit performance of downstream processes and reliability and can result in electrical failures. Plasma treatment can remove these contaminants, but the challenge has been to remove them in real-time, in high-speed, high-volume manufacturing environments, and to have a chamber and handling system to accommodate diverse wafer sizes and packages. This is especially true for 3D and wafer-level packaging processes such as fan-in, fan-out, wafer-level, and panel-level wafers and substrates. Nordson MARCH’s MesoSPHERE™ Plasma System, with its plasma confinement technology, solves those problems.
The MesoSPHERE is a plasma treatment system that enables very high throughput processing and can process 300mm wafers on frame and handle substrates up to 480mm. Its innovative handling system transfers round or square substrates and frame or bonded carriers. The modular design allows capacity increase on a per plasma chamber basis. Equipment front end module (EFEM) integration supports from 1 to 4 plasma chambers, while a pocket chuck design provides accurate substrate placement and centering for additional process repeatability.


Materials Supplier of the Year

Indium Corporation

Water-soluble fluxes have served as the typical industry standard for advanced packaging assembly for years. However, as the trend toward miniaturization continues to increase at a rapid rate, water-soluble fluxes pose significant challenges. Due to the required cleaning processes and tight spacing, flux becomes trapped or impossible to be cleaned away effectively.

Indium Corporation’s ground-breaking Ultra-Low Residue No-Clean Fluxes enables 2.5D advanced packaging manufacturers to eliminate the cleaning process, thus protecting the integrity of the solder joint which may experience excessive pressure/stress during cleaning.

Indium Corporation’s Ultra-Low Residue No-Clean Fluxes have a proven track record of solving numerous assembly challenges, such as preventing delamination caused by water-soluble flux residue leftover after cleaning, eliminating the cost of cleaners, and shortening the processing time.

soitec

Introduction by Soitec end of 2017 of latest generation of silicon-on-insulator (SOI) substrates in its Imager-SOI product line designed specifically for fabricating front-side imagers for near-infrared (NIR) applications including advanced 3D image sensors. The new SOI wafers from Soitec are now available in large volumes with high maturity to meet the needs of customers in the growing market for 3D cameras used in augmented reality (AR) and virtual reality (VR), facial-recognition security systems, advanced human/machine interfaces and other emerging applications.

Our newest Imager-SOI substrates represent a major achievement for our company and a smart way to increase performance in NIR spectrum domain, accelerating new applications in the growing 3D imaging and sensing markets. Innovative sensor design on SOI is achieved by leveraging our advanced know-how in ultrathin material layer transfer and our extensive manufacturing experience.

The new SOI substrate makes it possible to simply extend the operating range of high resolution silicon based CMOS image sensors into the NIR spectrum. This optimized version of SOI substrate greatly improves the signal to noise ratio in the NIR spectrum.

Semblant

Semblant has established itself as the global leader in protective nanocoatings in the electronics industry over the last 12 months. The company has seen rapid and widespread adoption of their MobileShield technology, a repeatable, sustainable, cost-effective nanocoating solution that protects mobile phones from water damage and corrosion, the leading causes of mobile devices. Consumers spent $23 billion repairing devices in 2017 alone.
Semblant is working with 9 of the top 11 smartphone manufacturers in the world to protect the world’s latest flagship mobile devices, having achieved Ingress Protection (IPX) 7 certification for MobileShield in 2017. IPX 7 verifies protection against the effect of water immersion at 1-meter depth for 30 minutes, providing consumers with the highest level of robustness and product assurance for their mobile devices, the only nanocoating company to do so. Over the past year Semblant has also opened a dedicated Customer Innovation Center in Shenzhen, China, home to the world’s leading smartphone manufacturers. The center is currently supporting Semblant’s growing partner and customer base in China, with the company having delivered high-volume manufacturing lines for its MobileShield solution in five facilities in China, including the top two smartphone contract manufactures in the world.
Semblant also expanded their nanocoating technology by launching CircuitShield, delivering sustainable, streamlined and cost-effective protective solutions for semiconductor devices and printed circuit boards (PCBs), bringing value to such applications as wearables, medical devices, automotive, aerospace and many more.

Brewer Science

Brewer Science (BSI) has been supplying advanced materials to the semiconductor market for over 37 years. For the last 13 years, BSI has been supplying temporary bonding/debonding materials that cover a wide variety of release methods, including chemical, thermal slide, mechanical, and laser release. These products provide the user with increased throughput, performance, and yield rates. BSI's wafer-level packaging materials enable device manufacturers to reduce the form factors and increase the efficiency of their products and processes. Brewer Science is committed to solving the biggest challenges in the compound semiconductor, 2.5D, 3D IC, and fan-out packaging markets.


Process of the Year

Adaptive Patterning, Deca Technologies

Adaptive patterning for wafer level fan-out packaging permits the shift of the die following pick and pack to be accommodated during subsequent processing thereby resolving yield issues that may occur due to the placement tolerance. A comparison would be to suggest wire bonding be accomplished with or without pattern recognition. Its efficiency results in the choice of pick and place capital to be more focused on the cost effectiveness rather than purely placement accuracy.

F.A.S.T.

F.A.S.T., by KOBUS, is combining the best of CVD and ALD deposition worlds: high deposition rate, high conformality, process flexibility, low process temperature performance & tool simplicity. Already demonstrating its uniqueness for TSV application, the F.A.S.T. deposition solution is becoming the reference when thick and conformal films are needed in applications such as advanced interconnects, photonics on IC, MEMS, 3D LED, µ-displays and much more. Moreover, it allows combining 3 deposition modes in one single reactor: PECVD, Pulsed PECVD, and PEALD. Forget about equipment compromises and select the best deposition solution to fit your device requirements. F.A.S.T. = ALD FILM PERFORMANCES AT CVD SPEED!

EV Group (EVG) Low-Temperature Laser Debonding Solution for FO-WLP

EVG’s next-generation low-temperature laser debonding solution combines a diode-pumped solid-state UV-wavelength laser and proprietary optics with a modular equipment platform to provide a universal, high-throughput and low cost-of-ownership (CoO) wafer debonding process optimized for FO-WLP. EVG’s proprietary optical setup shapes the Gaussian beam profile of the laser to achieve a highly reproducible beam with minimal heat introduced to the device wafer and excellent spatial control. This enables tighter process control, which coupled with the high pulse repetition rate of the laser leads to a well-controlled, high-throughput and low-temperature debonding process. Typical debonding can be achieved in less than one minute for 300mm wafers.

Building on years of experience in laser debonding, EVG’s breakthrough low-temperature laser debonding solution for FO-WLP also includes low laser maintenance, high carrier wafer lifetime, support for fully automated handling on film frame, oversized carriers or free-standing thin wafers, and optimized footprint layout—all of which contribute to the system’s low CoO advantages. EVG’s low-temperature laser debonding solution is based on the company’s open adhesive platform concept, which enables the use of a wide range of adhesives from various suppliers to give customers the most flexible choice of bonding materials.

Following its introduction in July 2017, several leading foundries and OSATs have successfully qualified EVG’s next-generation low-temperature laser debonding solution for FO-WLP.

Semblant

Semblant’s MobileShield delivers a proven, cost-effective solution to combat water damage and corrosion, the leading causes of mobile phone damage. With approximately 25% of smartphones being returned due to liquid and mechanical damage during use, repairing damaged smartphones costs the industry around $30 million per year.
MobileShield allows users to benefit from longer device life and the freedom to take their smartphones almost anywhere. For smartphone manufacturers, there are significant economic benefits; in addition to giving devices a first line of defense against common sources of damage, MobileShield coatings also enable repair at the component level. This substantially reduces device replacement expenditures for consumers, retailers and manufacturers alike.
Having recently achieved IPX 7 certification, protecting mobiles against the effect of water immersion at 1-meter depth for 30 minutes, the only nanocoating company to do so, MobileShield has seen widespread adoption by the world’s mobile makers in 2017. The company are currently working with 9 of the top 11 smartphone manufacturers in the world on its nanocoating technology, having delivered high-volume manufacturing lines in five facilities in China, including the top two smartphone contract manufactures in the world.

aveni

aveni's conformal Rhea copper seed was used in recent work at CEA-Leti, as part of the IRT Nanoelec 3D Program, for the fabrication of Through Silicon Vias (TSVs) at an unprecedented 12:1 aspect ratio. TSV aspect ratios have been limited to 10:1, due to limited reactant transport and slower deposition rates associated with conventional dry deposition methods, such as physical vapor deposition (PVD). These PVD constraints can lead to subsequent discontinuous or incomplete TSV filling, which affect reliability and electrical yield. The 12:1 TSVs (10µm diameter x 120µm high) using Rhea seed, achieved 100% electrical yield, with resistances that correlate very well to theoretical values. Electrografting™, aveni’s wet deposition technology, creates superior-quality metal layers, such as Rhea copper seed, which is instrumental to achieving higher aspect ratio TSVs.

Extreme Thinning for Lower Cost TSV (SPTS / imec)

Thinning wafers reduces the cost and technical difficulty of etching through-silicon vias (TSVs) in advanced “3D” packaging schemes. This has been the focus of a joint development project between imec, SPTS and other partners in order to optimize a “TSV-last” route for a multi-wafer stack using dielectric bonding and TSV interconnections.
Artificial intelligence, machine learning, even crypto currency mining is creating demand for High Performance Computing (HPC). Large interposers carrying GDU and 3D stacked memory cubes are starting to appear in server farms. For future stacked memories, workers are imagining how 32 or 64 memory wafers can be stacked together without breaking rules on stack height. Working with imec, SPTS has developed a Si thinning process to controllably thin the bulk Si to just 5um.
Thinning a whole wafer by dry plasma etching alone would be very slow and expensive, so this project opted to remove the majority of the silicon by more cost-effective grinding down to 50µm. The surface is then smoothed by chemical mechanical polishing (CMP) which removes only around 1µm of silicon, prior to a plasma-based blanket silicon etch to complete the thinning to the desired final thickness of around 5µm. The thickness of the thinned wafer must be uniform across the whole wafer to ensure the subsequent dielectric bonding and TSV formation steps are successful.
The joint project has demonstrated an optimized manufacturing route to thin, bond and connect up to 4 wafers, which eliminates the majority of the CMP processing resulting in a cost saving of around 50%[1]. SPTS’s Rapier XE silicon etch system was used in this project offering a high silicon etch rate >9µm/min and the ability to tune out the enhanced etching that naturally occurs at the wafer edge. A new end-point solution was also developed to control the plasma processing during the final stages of the thinning.

[1] “Extreme wafer thinning optimization for via-last applications”, A. Jourdain et al., IEEE International Conference on 3D System Integration - 3DIC, San Francisco, CA, 2016

Nordson

Product: MesoSPHERE Plasma System
Contaminants produced during semiconductor manufacturing often inhibit performance of downstream processes and reliability and can result in electrical failures. Plasma treatment can remove these contaminants, but the challenge has been to remove them in real-time, in high-speed, high-volume manufacturing environments, and to have a chamber and handling system to accommodate diverse wafer sizes and packages. This is especially true for 3D and wafer-level packaging processes such as fan-in, fan-out, wafer-level, and panel-level wafers and substrates. Nordson MARCH’s MesoSPHERE™ Plasma System, with its plasma confinement technology, solves those problems.
The MesoSPHERE is a plasma treatment system that enables very high throughput processing and can process 300mm wafers on frame and handle substrates up to 480mm. Its innovative handling system transfers round or square substrates and frame or bonded carriers. The modular design allows capacity increase on a per plasma chamber basis. Equipment front end module (EFEM) integration supports from 1 to 4 plasma chambers, while a pocket chuck design provides accurate substrate placement and centering for additional process repeatability.
Unique to the system is its patented W3 three-axis symmetrical plasma chamber which ensures that all areas of the wafer are treated equally and uniformly. Tight control over all process parameters gives highly repeatable results. The chamber design and control architecture enable short plasma cycle times with very low overhead for maximized throughput and minimized cost-of-ownership.

OmniVision Technologies' Nyxel™ Technology

OmniVision's new Nyxel™ technology for near-infrared (NIR) image sensing leverages novel silicon semiconductor architectures and processes to tackle the challenges plaguing NIR image sensors. OmniVision's approach to NIR imaging combines thick-silicon pixel architectures with careful management of wafer surface texture to improve quantum efficiency (QE), and extended deep trench isolation to help retain modulation transfer function without affecting the sensor's dark current. The result is an improved QE of up to 5x in OmniVision's latest image sensors, over all existing sensors in the industry. This allows them to see better and farther under the same amount of light, extending the detection range and reducing the number of LED lights for lower power consumption. Image sensors with Nyxel technology are ideal for any imaging application that operates in low or no light, including security cameras, machine vision, automotive, medical and mobile.

Brewer Science RDL First - Fan Out

Brewer Science has developed a laser release material that can help meet all of the critical requirements for sacrificial materials in the RDL-first process. This material is not only for adhesion and release, but can also serve as a foundational material upon which all the other materials are built. This new laser release material is compatible with both wafer-level and panel-level coating techniques.


Research Institute of the Year

Fraunhofer IZM

Last year, Fraunhofer IZM launched a consortium to bring research and industry together on all questions of implementing Panel Level Packaging in industry settings. Their aim was to accelerate standardization, develop a low-cost, industry-ready reference process and channel ongoing research advances into industry as quickly and efficiently as possible. Progress to date has been good, and the Fraunhofer IZM activity in the PLP space has received much notice.

A*STAR

A*STAR’s Institute of Microelectronics (IME) has established a development line to accelerate the development of fan-out wafer level packaging (FOWLP) capabilities for next-generation Internet of Things (IoT) technologies. The FOWLP development line, which is built upon existing infrastructure at IME’s facilities at Singapore Science Park II, and its new facilities at Fusionopolis Two, will allow IME and its partners to develop technologies that serve a wide range of markets such as that of consumer electronics, healthcare and automotive.

S3IP / Binghamton University

S3IP brings together teams of experts from industry and the University to address pressing real-world problems in the systems integration and manufacturing of electronics. Our research centers focus on topics related to electronics packaging, flexible electronics, energy-efficient data centers and energy harvesting and storage. S3IP, now celebrating its first decade as a New York State Center of Excellence, and its constituent research centers have contributed more than $1 billion in economic impact to New York State since 1996.
Binghamton University, the premier public university in the Northeast, is home to S3IP. We have a new $30 million building with unique laboratories and conference facilities at the University's Innovative Technologies Complex. Our PhD-level staff members and affiliated faculty are ready to assist companies in New York State and beyond with collaborative problem solving. S3IP's team tackles projects and addresses industry-driven research needs with efforts that may last a few hours or span several years, according to our partners' needs and interests.

Fraunhofer EMFT

Demonstration of high-performance communication:
Fraunhofer EMFT developed a novel specific fine-pitch 3D-TSV technology for RF IC and RF MEMS applications in cooperation with EPFL and IMEC.
Demonstration of Low-Temperature 3D Integration Processes for Advanced Sensor Systems:
Fraunhofer EMFT demonstrated advanced 3D detector/IC systems: read-out-circuit dies connected by Solid-Liquid Interdiffusion (SLID) to sensor wafer in cooperation with Max-Planck-Institute for Physics.


Startup of the Year

USound

MEMS micro-speakers, highly miniaturized, efficient, and high performing solution leveraging the advantages of piezo-actuation.

KOBUS

Based on FAST technology, KOBUS has developed a unique deposition solution to leverage the integration cost issue of TSV. With thick and conformal capabilities, our solution offers unique film properties at low temperature allowing for a drastic reduction in film thickness requirements, and thus can be extended to very high density and high aspect ratio features (> 20:1). There is a 25% reduction of integration cost, thereby dividing by two, the total Cu removal thickness before CMP. One tool answers both via middle and via last TSV integration requirements.  Relaxed via opening etch step results in conformal engineering along the TSV shape. Insensitivity to scalloping dimension variation.