For single die packages, electrostatic discharge (ESD) is well understood, and precautions are taken to minimize the possibility of charge build-up and ESD strikes. In single die designs, Input-Output (I/O) cells contain robust ESD protection circuitry. Additionally, ESD precautions are considered throughout the design, development, fabrication, and assembly/test of devices.
As we move toward more dense, vertical packaging, opportunities and challenges exist. Opportunities include smaller footprint, more tightly integrated design, increased performance and decreased power. Some of these improvements occur through use of less restrictive I/O cell design. In a 3D IC package, chips are closer together, there are thousands of interconnects, and I/O cell drive strength requirements are significantly reduced. With the majority of interconnects going within the 3D package (die-die), the possibility of an externally triggered ESD event is reduced. Thus, many I/O cells can have significantly reduced ESD protection or perhaps no protection at all.
This new packaging paradigm still requires a thorough understanding of potential ESD events, how to minimize the possibility, and how to react should an event appear to have occurred.The Global Semiconductor Alliance 3D IC Working Group, in collaboration with GSA member companies and the the ESD Association set out to address the issue of ESD in 3D IC packages, and its impact on 3D IC designs vs. single die ESD design, assembly and test, through detailed exploration and analysis. This paper addresses various stages of the development cycle, for chips designed to be used in a 2.5D/3D package. For each development stage, challenges, opportunities, potential ESD threats and countermeasures are discussed and compare with individual die development.
This White Paper was first published here by GLobal Semiconductor Alliance 3D IC Working Group, For more information, and to request a copy of the Xilinx ESD Case Study referenced in the paper, contact Harrison Beasley.