3D ASIP 2014 Pre-Conference Symposia Place Emphasis on 3D Design Tools and Flow, and Manufacturing Process Technology

3D ASIP 2014 Pre-Conference Symposia Place Emphasis on 3D Design Tools and Flow, and Manufacturing Process Technology

As 3D integration processes move into volume manufacturing, the 11th Annual 3D Architectures for Semiconductor Integration and Packaging Conference (3D ASIP), which takes place December 10-12 in San Francisco, is gearing up to be the go-to event for this hot market sector. With an expanded full-day pre-conference symposium on design and manufacturing for practical 2.5D and 3D implementation in addition to two days on the latest in technology and market developments, attendees will be brought up-to-date on the industry’s progress across the entire ecosystem.

Herb Reiter, eda2asic ConsultingOrganized and moderated by Herb Reiter, president, eda2asic, the pre-conference symposium morning session, 2.5/3D-IC Design Tools and Flows, sponsored by Mentor Graphics, features presentations by Bill Martin, eSystem Design; Zafer Kutlu, GLOBALFOUNDRIES; Brandon Wang, Cadence; Norman Chang, Apache Design; John Ferguson, Ron Press, John Park, Mentor Graphics; Ming Li, Rambus; Durodami Lisk, Qualcomm; and Jerry Frenkil, Si2.

“A major difference between this year’s 3D ASIP conference and those held in the previous 10 years is the heavy emphasis on 3D design and verification tools,” said Reiter. “After completing many evaluation units in recent years, both manufacturers and customers need the support of EDA tools to walk the fine line between costly over-designs and unreliable under-designs, when implementing 2.5D or 3D-ICs for volume production.”

philgThe afternoon session, 3D Integration: 3D Process Technology, organized and moderated by Phil Garrou, IEEE Fellow and Consultant, takes a quick look at the current status of the 3D marketplace, followed by a more detailed look at the status of the 3D TSV-based processing technology. This session, sponsored by Invensas, includes presentations by Phil Garrou, IEEE Fellow and Consultant, Microelectronic Consultants of NC; Dean Malta, RTI International; Severine Cheramy, CEA-Leti; and Laura Mirkarimi.

“With all three memory suppliers announcing TSV stacked memory architectures in 2014, it is more important than ever to understand the design and manufacturing technologies available for 2.5 & 3D production,” said Garrou.

Register today to attend 3D ASIP 2014. Visit 3dasip.org for a complete agenda and full conference details.