After wrapping up a run of blog posts from two weeks of travel and 4 conferences,(IWLPC 2012, the IEEE 3D Test Workshop, and MEPTEC’s co-located Roadmaps to Multi-die Integration and Known Good Die Symposium) it’s time to catch my breath and see what else has been going on in the 3D blogosphere.
From the looks of Phil Garrou’s SST post, I missed out on hanging with “many of the world’s 3D IC elite” at the 2nd annual Georgia Tech 2.5D Interposer Conference (November 14-16) It’s a good thing he was there to cover it, because the rest of us were at the MEPTEC events, scheduled the same days, and there are now so many 3D focused conferences, we can’t all be everywhere at once now can we?
Garrou relayed the conference takeaways, which seem to focus mainly on determining the market and application segments for silicon, glass and high-density organic interoposers, based on cost.
Its great to hear the news out of Alchimer once again. The company has gone dark for the better part of a year while it went through some major management shake-ups. The latest, reported here by James Montgomery in Solid State Technology, Semiconductor industry veteran, Bruno Morel, formerly of Applied Materials, Lam Research, Novellus, and Semiconductor Tooling Services was named CEO last spring, and long-time Alchimer product development director, Frédéric Raynal has been promoted to CTO and VP of engineering. The company is reportedly seeking partnerships with equipment and materials suppliers to further the advancement of its wet deposition process technology (“electrografting”) across multiple application spaces.
Before this announcement, the latest we heard from Alchimer was about its TSV barrier film advance in September of 2011, after a flurry of announcements throughout 2011. Here’s the back story on Alchimer, from when I visited the company in 2009. I look forward to learning more as the Alchimer enter’s its next phase with this new management team.
It looks like there’s another 2.5D FPGA game in town besides Xilinx. Reporting on a keynote address from last week’s Roadmaps to Multidie Integration and Packaging, given by by Anwar A. Mohammed, a senior staff scientist for packaging working in Huawei’s U.S. R&D center, EETimes Rick Merrit writes here that after speinding “more than a year evaluating as many as nine approaches before selecting the 2.5-D silicon interposer, Huawei is working with Altera, Tezzaron, eSilicon and Singapore’s Institute of Microelectronics to package an FPGA and a Wide I/O memory. Here are the details.
I keep running into SemiMD’s Mark LePedus at various industry events. We tipped our hats at each other at both IWLPC and the MEPTEC events last week. I’m always happy to see him covering things because it means there will be something interesting to curate, and he generally picks different topics to focus on than I do. At IWLPC, he interviewed Peter Ramm, of Fraunhofer’s EMFT in Munich, where there is a vital 3D heterogeneous integration program based on interposer technology. (Don’t call it 2.5D around Ramm.) Ramm explains the program to LePedus in this interview, where he highlights development in thick interposers as an alternative to thin interopsers, and also expands on one European project he’s spearheading, eBRAINS.
Another great read by LePedus is Mobile Memory Madness, where he talks about JEDEC’s new roadmap for mobile memory, and how it “ has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architecture until 2015. There’s a great brief history of Wide I/O, and what’s coming next, with commentary from Pat Moran, Qualcomm, Niranjan Kumar, of Applied Materials, Jung-Yong Choi, of Samsung, and Sunil Patel of GlobalFoundries.
And that about wraps it up for this week. Tomorrow is Thanksgiving, and I’m taking a few days off. Happy Thanksgiving to all! ~ FvT