Long before he set out on the 3D Holy Grail, Herb Reiter had other pursuits that involved bringing new technologies to market. Most notable is his work with field programable gate arrays ( FPGAs) and application specific ICs (ASICs), which, according to Reiter, actually started out as customer specific ICs (CSICs). Therefore, Herb has some reference points to draw from that I lack. So I regularly pick Herb’s brain, and he’s happy to oblige. Just last week, we had a conversation about the different messages being heard about the status of 3D integration, and the psychology behind it. It got me to thinking about why there still seems to be such diverging perspectives with regard to the commercialization of 3D ICs.

The Players in 3D
On the one hand, we have people like me, who are enthusiastically shouting from the mountaintops that 3D IS HERE! These declarations are based on messaging from companies like TSMC, Xilinx, Altera, Qualcomm and others, who have announced such news from many podiums at many industry events, and through marketing press releases. The remaining challenges are acknowledged, but can be engineered out fairly easily, they claim, (as long as they don’t add to the cost of ownership.)

Then there are the IDMs like Intel, IBM and Samsung, who clearly see the technology advantages of 3D ICs stacks, but at the same time are expressing grave concerns about the remaining hurdles. Because these companies operate almost entirely in stealth mode, it’s anyone’s guess what’s really going on behind those tightly sealed doors. If you think about it, there’s no motivation for them to share their secrets and encourage the rest of the industry to start competing with them. Rather, being first will give them the competitive advantage and allow them to enjoy a year or two of leadership. (Apple should be included in this group, but since the company doesn’t actually manufacture ICs, I didn’t include it.) If the rest of the industry continues to drag its collective heels, they’ll be rolling out product in volume as fast as you can say, “eat my dust.”

And then are those charged with solving the remaining challenges, the equipment manufacturers, EDA tool and test vendors who are trying to meet the growing demands of the customers while ironing out final process challenges. Those who have invested and are further along than others sing a much more optimistic song than those who are still struggling to grab their piece of the pie. These are the folks who opted to play it safe in the early days to see how the customers would respond.

The Pain of Change
As Herb explained it, whenever a disruptive technology is introduced, the first questions are always around whether the benefits are worth the pain of changing. With 3D IC, it’s becoming clearer that the value proposition and benefits will be very compelling. “Hopefully soon someone will introduce a real product with a 3D stack that is twice as fast and uses half the power, compared to a traditional SoC implementation” Herb said, “then the technology will be taken seriously.”

The DAC Panel
Our conversation turned to its original purpose, which was to update me on the recent 2.5D and 3D panel held at DAC, which we both agreed had been more than adequately covered by Richard Goering, in his post, Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs. (You might recall that I also referred to this post in last week’s curated article.) Panelists included:

  • Shekhar Borkar, director of extreme scale technology, Intel
  • A.J. Incorvaia, vice president of R&D for the Cadence PCB and IC Packaging group
  • Subramanian Iyer, fellow at IBM Systems and Technology Group
  • Suk Lee, director of design infrastructure marketing, TSMC
  • Liam Madden, corporate vice president of FPGA development, Xilinx

(Incidentally, it was Goering’s choice of the word ‘contentious’ that sparked the topic of this blog post, along with the general takeaway that while “2.5D technology is very close to volume production, true 3D stacking raises some issues that still need to be resolved.”)

Herb added some key observations of his own. First, he noted that overall, the panelists for the session were real experts and respected leaders in their field. He can’t argue with any of the comments, he said, because they provided a very realistic and professional assessment of where we are in the 3D ecosystem.

He said he finds it interesting that Intel and IBM (at least for internal purposes) are targeting 3D stacks. For Intel, it’s a matter of not incurring the cost of the interposer for high value manufacturing. For IBM it’s the advantages true 3D bring to the server business. He noted Intel’s Shekhar Borkar comment that it’s all about form factor for Intel, and IBM’s Subu Iyer stating that power reduction is the key motivator for IBM to go to 3D.  Conversely, on multiple occasions, Liam Madden of Xilinx declared that 3D is nice, but 2.5D is much easier with regards to ecosystem partners and power and heat management.

He also found it interesting that for once, panelists did not talk too much about cost.  There was, however, discussion about the emerging business model, and debate about what foundries and OSATS are doing and who takes how much of the profit margin.

Madden stressed the importance of 3D DRAM stacks, and that the memory suppliers need to deliver cost effective 3D stacks because going forward, all applications need tons of memory and there is a supply bottleneck. He also stressed that for SOC design, there is a need for  design kits ( similar to PDKs) that contain all capabilities of the supply chain in regards to wafer fab, interposer generation, packaging capabilities, and test considerations, and that today’s 3D PDKs only represent first baby steps. Suk Lee agreed that PDKs are important, and that PDKs need to be put in place especially for thermal and pathfinding.

Test is Underrated
The topic of test came up, which according to Herb, is the most critical and underserved technical challenge in the 3D space at the moment. “I’m not talking about design for test (DfT),” he clarified. “The real worry is with test equipment, as manufacturers realize 3D stacks bring added complexity and limited ability for access. Do we need to test partial stacks or will economics speak against interim testing?”

Herb notes that yield and cost management is a big challenge coming our way on the production floor, and he hopes Advantest and Teradyne will address 3D test challenges soon. He pointed to the Memory space as being likely first to have test solutions, and that ongoing efforts there may give our industry enough expertise so that the test floors will get ready for heterogenous stacks as well. He stressed the need for redundancy designed into the 2.5 and 3D configurations. We may find having a very high yield without redundancy is not really economically feasible. The 3D expert panelist at DAC also stated that redundancy is under-represented, and that 3D stacks are subsystems rather than ICs, and we have to start thinking on a system level; every reliable system has redundancy built in.

Also with regard to yield, Iyer noted that we want to move away from stacking die to wafer, because wafer to wafer stacking allows for more accurate alignment, and the ability to stack so many die at one time cuts down on machine time and with it, cost. In that case, a manufacturer can take a reasonable yield hit without crying about cost problems.

Academia’s Role
An interesting question posed by the moderator was what can academia do to accelerate 3D adoption? He was likely expecting to hear about R&D opportunities, but what he got was a frank response from Iyer, to “crank out more PhDs!” with knowledge of 2.5D and 3D design. There are millions of jobs open, but a qualified pool of applicants is apparently hard to come by.

The Fear Factor
Circling back to the original topic of this blog post, Herb noted that when the panel asked what’s been overhyped, and portrayed as a big problem, the response by Madden was fear, uncertainty and doubt (FUD).This acronym has been heard by Herb many times in the good old ASIC days. He says it’s not necessary to be as afraid of this new technology as so many people currently are.

With SEMICON West fast approaching, keeping all this in mind as you attend sessions and listen to what’s being said might help put it all in perspective. ~ F.v.T.

Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

View Francoise's posts

Become a Member

Media Kit

Advertising

Login