Francoise von Trapp

They call me the “Queen of 3D” because I have been following the course of…

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Ok, I realize it’s not really the New Year, but for me, September is always about beginnings. The school year gets underway on most continents (except in Arizona, where its been in full swing for three weeks). It marks the end of summer holidays in Europe (Is August also holiday season in Asia? I need to find that out.) Most importantly, my semiconductor career began in September. So its really no surprise that in the flip of a calendar page, industry news went from a trickle to a steady stream. It’s time to get back to business. Here are a few highlights that caught my attention.

It looks like S.E.T. has completed the trifecta with another R&D order for its high-accuracy and high force Device Bonder FC300 system. This time the tool is headed for placement at SEMATECH’s 300mm lab at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex in Albany, N.Y. SEMATECH will use the tool for its 3D Integration program, initially for evaluation of die-to-wafer bonding applications, and later for die-to-die bonding. The FC300 has already been installed at both IMEC and CEA-Leti, most likely because it’s the only R&D level device bonder that can achieve required accuracy. The next step will be a tool that can achieve high accuracy at volume speeds.

We continue to see slow but steady headway with design and test issues. Certainly, the fall line-up of events covering 3D integration reflects more participation from the design and test communities than past years. Most notably, the larger design houses such as Cadence and Mentor Graphics are coming forward, which is a good indicator that we’re getting closer.

Case in point: the IEEE 3D Systems Integration Conference, (San Francisco, Sept 28-30) drew enough participation from both industry and academia to fill two sessions dedicated to CAD topics and one session on design methods. Participating companies from the design space include Cadence, R3Logic and Mentor Graphics, in addition to internal work on design solutions from Renesas, Qualcomm and IMEC. The Test, Thermal, and Power Delivery session still consists mainly of contributions from academia – in general, and indication that there’s a ways to go before test solutions will be available for volume production.

Or is there? Just today, SUSS MicroTec added to its 300mm tool offerings targeting 3D integration by launched its probe station PA300PS 3D, designed for electrical probing of 3D stacked structures at the wafer level. The flexible probe station reportedly allows for various engineering and monitoring tests after wafer production and prior to further stacking or final packaging. This news follows last week’s announcement that SUSS is expanding its 3D presence in Japan, with the installation of its LithoPack300 lithography cluster, which will be used for 3D integration technology development. This all plays into SUSS’s strategy to provide a soup-to-nuts turnkey solution. Looks like its working.

Lastly, Yole Développment just released its 2009 report on Memory Applications, Packaging & Integration Trends. Yole’s findings indicate that the growing world of wireless communication has created new drivers for 3D integration; namely connectivity and integration; and what better way to achieve this than through 3D IC stacking with TSVs? They estimate 20,000 3D TSV stacked DRAM memory wafers will ship by the end of 2009, with higher volumes expected in 2010. Yole predicts that by 2013, the telecom and computing industries will drive more than 70% of the volume for 3-D TSV integrated memories. According to Yole, it’s lift-off time. — F.v.T.