3D Integration 101: Explore, Learn, Share

Save the date for the SEMI 3D & Systems Summit, to be held January 27-20, 2020, in Dresden, Germany, where top experts will gather to

High-performance computing (HPC) has become an important tool for areas that generate high volumes of data. While today’s HPC is already powerful, many scientific and industrial challenges require even more computing power, for instance, drug discovery and material design. Thus, the global drive for exascale (1018) computing.

Severine Cheramy, Director 3D Business Development, at CEA-Leti, recently brought key partners of Leti’s 3D-IC programs together at the 6th 3D VLSI Open Workshop to

Tomorrow evening (Nov. 7, 2019), Dr. Mary Jane Irwin will take the stage at a dinner being held in her honor, as she becomes the

We hit the exhibits at IWLPC 2019 with a vengeance this year. Our mission was twofold – to find out the latest supplier offerings to

Co-located with productronica in Munich, Germany, SEMICON Europa attracts and connects industry-leading technology companies from every segment of the European microelectronics industry. Held November 12-15, this year’s

“The die-attach equipment market is showing a 6% CAGR between 2018 and 2024”, announces Santosh Kumar, Principal Analyst & Director Packaging, Assembly & Substrates, Yole

At IWLPC 2019, the fan-out panel-level packaging (PLP) debate continued in another of Jan Vardaman’s famous lively panel discussions, which was co-moderated by PLP technology

At MSEC 2019 in San Diego, CA, MEMS and sensors experts gathered to exchange ideas about how to utilize the many strengths microelectromechanical systems (MEMS) and sensors to enhance the capabilities of electronic systems. Many focused on adding AI to their devices to provide higher-value solutions.

At last week’s IWLPC 2019, Three keynotes by industry thought leaders provided perspective on the current climate of the semiconductor industry, and how best to weather the storm to set your company on a path for success.

I’m a huge baseball fan. And while my favorite team, the Arizona Diamondbacks didn’t even make it into the playoffs, it doesn’t mean I’m not

Samsung Electronics has announced the development of 12-layer memory using 3D through silicon via (3D-TSV) chip packaging technology. TSVs vertically interconnect the two DRAM chips through more than 60,000 TSVs. Despite the increase in the number of layers from eight to 12, the overall thickness of the package remains at 720 µm so designers will not have to change dimensions to use the new technology. Samsung will soon be able to mass-produce such 24Gb high bandwidth memory (HBM), which will provide 3X the capacity of 8GB HBM on the market today.

Adjusting or repairing some of the sprinkler heads on my lot is a regular Spring duty for me. This year, when I was working on

Remember when panel level processing was called large-area processing? Here, Phil Garrou provides a history lesson beginning from when he and Ted Tessier first presented the concept, to today’s progress.

The Electronic Design Process Symposium – EDPS 2919 – is known in the IC design community as a rather small (50 – 100 participants), but

Anyone who’s anyone with a hand in the evolution of wafer-level packaging will be in attendance or exhibiting at the 16th Annual International Wafer-Level Packaging