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Written by and for the design community, 3D by Design features thought leaders who understand the benefits of designing in 3D and have been instrumental in the commercialization of 3D integration technologies.

DAC2016part2

DAC 2016: There is More to Life than IC Design, Part 2

Part 1 of my DAC 53 reporting focused on this year’s really impressive keynotes, now posted on the DAC website, together with videos of other remarkable pavilion presentations, panels, interviews, demos, etc.…. Part 2 will cover a few highlights that I found very interesting and useful at DAC. Considering that this blog is being posted on 3D InCites, let’s talk about CEA Leti’s 3D network-... »

DAC2016

DAC 2016: There is More to Life than IC Design

In the past, the Design Automation Conference was known to me and many of my colleagues as the annual event that focused on IC design tools, flows, and methodologies. EDA tools vendors and users got together in the previous millennium to discuss what to do next in a rapidly growing market segment. Then things changed… At the beginning of this millennium, the wafer foundries took charge of silic... »

moore workflow summary-4 workflow

Challenges and Solutions for EDA of 3D Chip Stacks

It is often claimed that 3D chip stacks offer the potential to meet current and future requirements of digital circuits, such as for performance, functionality, and power consumption. Specifically, both design paradigms “More Moore” and “More than Moore” will benefit from 3D chip stacking (and new technologies and materials). 3D stacking enables notably reduced interconnect... »

Figure 1. Standard wafer test. Figure 2. 3D test. Hybrid test. 3D IC memory BIST

3D IC Test: Now and The Road Ahead

Solutions for 3D IC test are ready today, but they will be more ready tomorrow. At the 2015 ISTFA, I presented a tutorial titled “What is New in 3D, Digital Testing?” and I’ll summarize the main points here. I consider test standards and test challenges, which include known-good-die and testing stacked die. The two main goals of 3D IC test are to improve the pre-packaged test quality and to ... »

riko

Intercepting IC Products with a Disruptive Technology Option

Much has been written about the challenges that corporations face – especially established corporations – in adapting to a disruptive technology and the associated paradigm shifts. Most of the tomes on the subject focus on corporate management strategies. My intent is to discuss these challenges from a technology point of view – specifically when it comes to adopting so-called 2.5D and 3D d... »

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DesignCon 2016: Where the Chip meets the Board and Great Ideas Come to Life

DesignCon 2016 at the Santa Clara Convention Center gave football fans among us an opportunity to watch the preparation work for Super Bowl 50. Right across the street from the Convention Center is Levi Stadium, where on Sunday, February 7, this year’s champion will be crowned. Impressive, but let’s not digress and focus on DesignCon. For me, in my role as business developer for innovative pro... »

needleinhaystack

A Perfect Storm is Brewing for Complex Packaging in 2016

If I had not attended the 2015 3D ASIP conference, my outlook for 2016 would have been less upbeat for complex packaging (2.5/3D). But this conference showed that companies and their development organizations are NOT solely looking towards FinFETS and sub 20nm silicon process nodes to meet their integration, power, speed, weight, etc metrics.   We are in the perfect storm: out of control costs a... »

‘Tis the Season for the 3D ASIP Multi-Die IC Design Tutorial

While the shopping malls and specialty stores in and around San Francisco were packed with people hunting for Holiday presents, a very dedicated crowd of 3D IC developers and users from all over the world got together near San Francisco, for the 12th 3D ASIP conference, which featured, once again, the multi-die IC Design Tutorial. Conference presenters reviewed the progress made in 2015 and discus... »

tarek

Why Do We Need Assembly Design Kits for Packages?

In our last article, we talked about a project we participated in to test the feasibility of an assembly design kit (ADK) for package design verification. This time, we’d like to delve a little more into the reasons why assembly design kits are needed. Naturally, one of the reactions to our article was “But I already have requirements from my package house. Why do I need an ADK?” True, packa... »

PDNfig1 PDNfig2 PDNfig PDNFig3

PDN Noise: PDN and Signal

In a previous blog, I discussed a power design network’s (PDN) self and transfer impedances. Self impedance highlights anti-resonances causing a significant increase in the PDN’s impedance. The anti-resonances increase a design’s power, noise, and lessen performance. Transfer impedance shows the change in impedance from one location to another on the PDN structure. The higher transfer i... »

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