With the increasing popularity of multi-chiplet designs, EDA companies have had to innovate to provide integrated and IC-centric tools. These advanced tools build accurate system-level models that find the fastest and most efficient path for 3D-IC design and analysis.
Join our CadenceTECHTALK series and learn how to properly plan and implement stacked digital SoCs, analog/mixed-signal designs, and entire 2.5-D/3-D systems, including meeting system-level power and thermal analysis requirements through an integrated 3D-IC solution. This series will cover:
- February 23: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
- March 9: System Planning and Implementation for Different 3D-IC Design Styles
- March 23: 3D-IC Chip-Centric Power/Thermal Integrity with High-Performance Hierarchical Analysis
- April 6: Overcoming System-Level 3D-IC Electrical and Thermal Challenges