The 3D IC Forum at SEMICON SIngapore 2014 takes place on Thursday, April 24, from 9:30-5pm. This year’s theme is Interposers and 3D Solutions for Low-Cost Heterogeneous Integration. Many companies have started introducing products built on 2.5D interposer and 3D IC technologies, and some are in production. A collaborative approach is necessary for the industry to successfully drive up the demand and manufacturing volumes for 2.5D/3D-ICs. To better understand challenges that are encountered and anticipated in high volume manufacturing (HVM), experts from fabless, IDM, EDA, Foundry, OSAT, equipment, and materials companies have been invited to share their perspectives as the industry enters the next phase of this evolution: achieving HVM and developing low-cost solutions for heterogeneous integration.
Chaired by Dr. Surya Bhattacharya, Director, Industry Development (TSV), A*STAR Institute of Microelectronics, this forum brings together leading Industry/Market Analysts, System manufacturers, Fabless companies, University, IDM, Foundry, OSAT, Equipment manufacturers and Materials companies to share their knowledge and insights.
Throughout the program, technology updates will be given by representatives across the supply chain including researchers, suppliers, manufacturers, and market analysts. The final Agenda has been posted
- 3D Packaging Technologies and Industry Trends, Ms. Rozalia Beica, CTO, Yole Développement
- 3D IC Equipment and Process: Challenges and Solutions, Mr. Yuichi Abe, General Manager, Assemble & Test System Business Unit, Tokyo Electron Limited
- Sub-20nm 3D IC Packaging Challenges, Mr. Ramakanth Alapati, Senior Manager, Package Architecture and Customer Technology Group, GLOBALlFOUNDRIES U.S. Inc.
- Heterogeneous 3D Integration Technology based on Reconfigured Wafer-to-Wafer Bonding, Dr. Mitsumasa Koyanagi, Professor, Tohoku University
- Orthogonal Scaling to extend Computing into the Cognitive Era KEYNOTE: Dr. Subramanian S. Iyer , IBM Fellow, Mcroelectronics Division, IBM Systems & Technology Group
- Challenges for the Development of Faster TSV and Cu/Sn Pillar Plating Chemistries, Dr. Bernd Roelfs, Global Product Manager, Atotech Deutschland GmbH
- 2.5/3D Integration –Moore’s Law and Beyond, Dr. Yoon Seung Wook, Director, STATS chipPAC Ltd.
- Making 2.5D/3D IC A Reality: A Market and Technology Update, Ms. E. Jan Vardaman, President, TechSearch International Inc.
- Manufacturability Considerations in 2.5D, Mr. Sitaram Arkalgud, Vice President of 3D Technology, Invensas Corporation
- Highly reliable Chip‐to‐ Chip Cu Wiring Technologies for 3D/2.5D interconnection, Dr. Tomoji Nakamura, Senior Expert, Devices and Materials Lab, Fujitsu Laboratories Ltd.
- Cost Effective Implementation of 2.5D /3D ICs, Dr. Surya Bhattacharya, Director of Industry Development (TSI), A*STAR Institute of Microelectronics
- Endpoint Controlled Via Reveal Etch Processes Targeting Improved CoO, Mr. Richard Barnett, Etch Products Marketing Manager, SPTS Technologies Ltd.
- Electrodeposition In The 3D World, Dr. Steve Mayer, Corporation Fellow, Lam Research
- Wafer Level Fan-Out as Fine-Pitch Interposer, Mr. Steffen Krohnert, Director of Technology Technical Marketing, Nanium S.A.
- Enabling Technologies for 2.5D Interposer Manufacturing, Dr. Thorsten Matthias, Director of Business Development, EV Group (EVG)
On Friday afternoon, and concluding the events, will be a Packaging & Test SEMI Standards Workshop (WLP/3DIC). The forum is titled: Industry Standards Efforts to Accelerate Next Generation Packaging and Test, chaired by Ms E. Jan Vardaman and Dr Timothy G.Lenihan (TechSearch International, Inc).
In Packaging, design houses, foundries, IDMs and OSATs have not agreed upon an industry-wide path toward 3D stacked ICs, delaying high-volume adoption. Consequently, Gartner currently forecasts that TSV devices will account for less than five percent of the units in the total wafer-level packaging market by 2017. Significant standards efforts are underway to address many of the challenges in 3DIC and are bringing together the industry to accelerate stacked IC adoption.Converging and collaborating would strengthen the supply chain and hence bringing down the cost of production in packaging.
In Test, since parallel testing has provides little significant changes in technology, and the next major transition will involve more advanced use of test data utilizing Adaptive Test and other “Big Data” concepts. This will require unprecedented test data sharing across the supply chain, requiring new industry collaborations and agreements that will require standard data protocols, hierarchies and APIs.
This forum will introduce and describe the industry-wide standards efforts in 3DIC and Test that will play a major role in facilitating these necessary transitions.
Forum Agenda: The intent is to identify area of standards so that the Singapore region can identify and start forming a Standards committee to gear up for industry and manufacturing readiness.
3D IC Standards Overview
3D IC Standards Status
- Thin wafer handlimg
- TSV Inspection and metrology
- 3D IC wafer bonding
- In Situ Interposer testing
- Partial stack testing
- 3D stack alignment strategy (front side, backside marking)
- Assembly flow D2D, D2W
In addition to a robust conference schedule, SEMICON Singapore’s Exhibits and Pavilions offer attendees a variety of learning opportunities as well as provide unique opportunities to engage with suppliers around customers.
. Visit SEMICON Singapore to for more information.