The semiconductor industry has come a long way from the days where the semiconductor die design / layout team simply passed the device off to another team to “handle” the packaging. Now there are packaging Design Integration (DI) teams who are responsible for “co-designing” the packaging and other processing while the chip is being designed. These teams resolve interdependencies, develop test vehicles, and manage risk to make sure there is a viable product.
Heterogeneous Integration (HI) of multiple semiconductor dies of different designs in a single advanced package to increase functionality has become commonplace. HI provides significant challenges to assembly and test today, and is Design Integration really ready to efficiently deal with HI? Especially as “Chiplets” – integrating an even larger number of die each smaller than a complete ‘standalone’ semiconductor device in a single package – gain traction these challenges will become even harder. Instead of a single digit number of die, assembly and test will need to accommodate tens of Chiplet die in each package.
As part of the MEPTEC Road to Chiplets series, we will discuss the role and challenges of DI in the upcoming storm of Chiplets. Properly implementing and developing methodologies to manage DI is essential to make Chiplets commercially viable.
Road Chiplets – Design Integration
May 10 – 12, 2022
| Tuesday | May 10, 2022 | 8:00 – 11:00 am PDT |
| Wednesday | May 11, 2022 | 8:00 – 11:00 am PDT |
| Thursday | May 12, 2022 | 8:00 – 11:00 am PDT |
