This year, the 18th IEEE International Interconnect Technology Conference (IITC) is combined with
the 24th Materials for Advanced Metallization Conference (MAM) from May 18 to 21, 2015, Minatec Campus, Grenoble, France.
Semiconductor Experts,
- If you plan to continue following Moore’s Law – by shrinking feature sizes to 10 nm or even below – OR
- if you need to pack multiple dice into one IC package – utilizing vertical stacking or interposer technology – OR
- if you want to increase system performance while reducing power dissipation – by deploying optical links – OR
- if you need to know about the latest advances in interconnect technology and materials for any other reason,THAN
You should attend the combined IITC 2015 and MAM conference, where experts in these fields will update you and answer your questions.
The technical program includes:
- More than 100 papers and poster presentations and offers networking time.
- Monday, May 18, is dedicated to Workshops, focusing on “Flexible Electronics” and “2D Materials for Interconnects” .
- Tuesday starts with the welcome note from Didier Louis, the European Chair of IITC/MAM, followed by a keynote address from Dr. Marie-Noëlle Séméria, Chief Executive Officer, Leti.
The rest of Tuesday, all of Wednesday and Thursday span the technical sessions and poster presentations.
The four papers listed below are examples for areas that will be addressed and show the level of sophistication you can expect from IITC/MAM:
- Intel will present:
“Low-k Interconnect Stack with multi-layer Air Gap and Tri-Metal-Insulator-Metal Capacitors for 14nm HVM”
and describe the technology as well as the benefits Intel reaps with this high-performance logic process - Toshiba will describe:
“Electrical Properties of 30 nm Width Bi-Layer Interconnects of Multi Layer Graphene (MLG) and Ni”
and share process information as well as results from their stacked interconnects. - TSMC will address:
“A Flexible Top Metal Structure to Improve Ultra Low-K Reliability”, and talk about delamination problems C4 bumps in flip-chips cause and describe an elastic material that reduces stress. - Intel will also talk about:
“Nickel Silicide for Interconnects” and describe methods for Nickel Silicide integration and its advantages versus copper.
Plan you trip, organize your conference schedule and book at hotel to attend this conference
Questions and/or further conference information needed?
Please contact WWalker@Widerkehr.com or Herb@eda2asic.com
