This month, the GSA 3D IC Working Group will explore system-level aspects of 3D IC Packaging. We hear from Cisco, nVidia, and Zuken on supply chain preparation, memory requirements, and system-level co-design.
3D-IC System Level Co-design
Faiza Ahmad, Zuken
The unique requirements of entry into new markets (automotive, wearable, IoT) is forcing companies to implement sophisticated package structures to realize the latest product platforms. To meet aggressive schedule and market requirements, engineering teams need to evolve from working in silos and within disconnected tool flows to new methodologies that enable them to collaborate across disciplines.
Using a system-level co-design approach in a 3D hierarchal design platform, engineers and architects are enabled to conduct path-finding studies and concurrent, detailed design of the chips, packages, and boards and access to analysis tools ensures designs are completed to meet electrical and physical and manufacturing specification. System-level co-design enables engineering teams to reduce time-to-market and product cost by eliminating frequent hand-offs in the design process and optimizing layer counts for RDL, interposer/substrates, packages, and PCBs.
Supply Chain Development for 3D ASIC and Memory Integration
Li Li, Cisco Systems, Inc.
To enable 3D ASIC and memory integration, several critical technologies need to be in place. These include the 3D Stacked DRAM, large size interposers and micro-pillar interconnects. In addition, innovation and development of the supply chain ecosystem to support the integration is of great importance. In this talk, we will review some of critical technologies. Discuss the potential disruptions to the existing supply chain and the development needed to fill the gaps.
Next-Generation Stacked Memory Systems
Alok Gupta, NVidia
Absolute power is not just a mobile issue and is a constraint for all designs. Logic power benefits from reduction in operating voltage and Moore’s law but memory IOs see little to no advantage from process scaling. To keep pace with increasing logic horsepower, memory bandwidth must scale within the same power budget else overall performance becomes memory bandwidth limited. New technologies and interconnects are essential to keep this balance and continue growing memory bandwidth. Next generation stacked memory solutions provide an alternative to traditional on-board memory systems while fulfilling demand for ever-growing need for higher memory bandwidth. These solutions are promising but come with unique technical and business challenges of their own. This presentation provides an overview of next generation stacked memory solutions and challenges associated with each of the solutions.