12/11/2013 - 12/13/2013 -All Day

Location: Grand Copthorne Waterfrong Hotel Singapore

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EPTC 2013 – the 15th Electronics Packaging Technology Conference is an International event organized by the IEEE Reliability/CPMT/ED Singapore Chapter and sponsored by IEEE CPMT Society.

Besides the technical sessions on 12th and 13th December 2013, there will be:

  • Keynotes deliberating on technology trends/advancement by Mr Mike Leary (Vice President of Mixed Signal Design, Xilinx, USA) who will present, “Heterogeneous 3-D Stacking, Can We have the Best of Both (Technology) Worlds”? and Toru Ogawa (Director -Backend Business Division, TSMC) who will present, “Current and Future Prospect of Advanced Packages.”
  • An evening forum session on 11th December 2013 chaired by Dr John Lau (ITRI Fellow, Taiwan) titled “Supply chain Integration in 2.5/3D packaging” by experts covering 2.5/3D technology trend, Frontend-Backend integration, Business model & value supply chain and most importantly, OSATs’ high volume production readiness.
  • Great learning opportunities in short courses and new developments in industry through exhibitors.

Conference Topics:

  • Advanced Packaging: Flip-chip and wire-bond packaging, embedded passives and actives on substrates, 3D System in Packaging, etc.
  • TSV/Wafer Level Packaging: Wafer level packaging, embedded chip packaging, 3D integration, TSV, Silicon interposer, RDL, bumping technologies, etc.
  • Interconnection Technologies: Wire-bond technology, Flip-chip technology, solder alternatives (ICP, ACP, ACF, NCP), die attachment (Pb-free), etc.
  • Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, photo voltaic, printed electronics, wearable electronics, etc.
  • Materials & Processes: Materials and processes for traditional and advanced microelectronic systems, MEMS, solar, green and biomedical packaging.
  • Electrical Modeling & Simulations: Power plane modeling, signal integrity analysis of substrate/package.
  • Mechanical Modeling & Simulations: Thermo-mechanical, moisture, fracture, fatigue, vibration, and drop impact modeling, Chip-package interaction, etc.
  • Thermal Characterization & Cooling Solutions: Thermal modeling and simulation, component and system level thermal management and characterization
  • Quality & Reliability: Component, board and system level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc.
  • Wafer/Package Testing & Characterization: High-speed test architectures and systems design, test methodologies, probe card design, package-test interaction, high-throughput testing etc.

For the full program and to register, visit the EPTC 2013 website