03/13/2015 -All Day

Location: ALPEXPO

Loading Map....

Workshop on 3D Integration – Applications, Technology, Architecture, Design, Automation, and Test

Now in it’s seventh year, the Friday 3D Integration Workshop, which takes place March 13, 2015 in Grenoble,  France, is part of the Design, Automation, and Test in Europe (DATE) conference and exhibition. The workshop program consists of a plenary keynote, regular and poster presentations, and a panel session. It aims to enable scientific discussions on challenging issues related to 3D integration, through quick and valuable feedback on work-in-progress related to the topics covered by the call for papers.

DATE is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. DATE 2015 takes March 13-15, 2015, in Grenoble, France.

The 2015 Workshop on 3D Integration Agenda Highlights

  • Keynote by Paul Franzon, NCSU, on “Computing in 3D.” Abstract: 3DIC technology refers to stacking and interconnecting chips and substrates (“interposers”) with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. At NCSU, we have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Main memory redesign, using both DRAM and RRAM, is explored to show potential for an order of magnitude reduction. Possible extensions to Cortical Processing are discussed.
  • Special Session: “3D Memories”
    Chair: Christian Weis, Microelectronic System Research Group, DE, Contact Christian Weis
    What are current 3D memory technologies offering? This special session will put a spot on high-bandwidth proximity IOs, the influence of 3D memory on computing and real facts about 3D memories.
  • Invited Talk and Panel
    Moderator: Françoise von Trapp, 3D InCites, US

    • Invited Talk: “Testing of 3D ICs: Hype, Myths, and Realities” Speaker:  Krishnendu Chakrabarty, Duke University, US
    • Panel: “Will 3D Integration Break Down Memory Bandwidth Barriers? How and When?”  Abstract: It’s official. Memory has moved into the interposer and 3D stacked IC space with many companies announcing stacked Memory products for high-end computing applications including networking, data servers, and gaming. But does this solve the memory bandwidth issue across the board? Will we see similar memory stacks in consumer products? And if so, what has to happen? What requirements transpire for TSV-based interconnects and interposers? This provocative panel (with interactive audience participation!) will offer perspectives from R&D, manufacturing, and end-users.
      • Panelists: Brendan Farley, Xilinx; Denis Dutoit, CEA-Leti; Hsien-Hsin S. Lee, TSMC; Mustafa Badaroglu, Qualcomm; and Geert Van der Plas, imec
  • Special Session: “Die-package Co-design Benefits and Challenges” Chair: Herb Reiter, EDA2ASIC, US, herb@eda2asic.com
    Interposer and 3D-IC designs pack more functionality into a smaller space (cm3). While saving total power dissipation (in Watts) they significantly increase power density (in Watts/cm3). To keep the junction temperatures of the closely packed dies within limits and guarantee functionality, parametrics and reliability, all at an acceptable unit cost, the IC package and its components play a major role. Only by considering the package characteristics already during the IC design process, an optimal solution can be found. Close cooperation between EDA tools developers, IC designers and IC manufacturers is required to develop and agree upon a user friendly and cost-effective die-package co-design environment. The presenters will detail the current challenges and outline key benefits of an emerging die-package co-design methodology.

For the detailed agenda and to register, visit the Friday Workshop on 3D Integration page on the DATE 2014 Website

DATE Workshop Organizing Committee 

Saqib Khursheed – General Co-Chair
University of Liverpool, UK

Pascal Vivet – General Co-Chair
Grenoble, FR

Christian Weis – Program Co-Chair
TU Kaiserslautern
Kaiserslautern, Germany

Andy Heinig – Program Co-Chair
Fraunhofer IIS, EAS
Dresden, Germany

Steering Committee Members:
E. J. Marinissen – IMEC (BE)
Q. Xu – Chinese U of Hong Kong (HK)