3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. With the limits of current sub-nanometric technologies, 3D integration technology is paving the way to a wide architecture scope, with reduced cost, reduced form factor, increased energy efficiency, allowing a wide variety of heterogeneous architectures. Due to the high amount of required data and associated memory capacity, ML and AI accelerator could benefit of 3D integration not only for HPC, but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also but also for next generation of computing architectures: AI accelerators, InMemoryComputing, Quantum, etc.
The 3D Integration Workshop took place in DATE conference from 2009 to 2015 and took place again in 2022. With the continued evolution of 3D technologies in terms of interconnect density and its evolving manufacturing eco-system, there is a strong need to pursue the research efforts on key aspects of architecture and design, according to the potential capabilities offered by 3D integration.
The goal of the 3D Integration Workshop is to bring together experts from both academia and industry, interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.
This half-day event consists of a plenary keynote, invited talks, and regular presentations.
DATE 2023 Workshop on “3D Integration: Heterogeneous 3D Architectures and Sensors”
Wednesday April 19, 2023
You are invited to participate and submit your contributions to the DATE 2022 Friday Workshop on
3D Integration. The areas of interest include (but are not limited to) the following topics:
- 3D technologies: chiplet, interposer, through-silicon-vias, micro-bumping, hybrid-bonding, monolithic 3D
- 2.5D/3D architectures and partitioning for logic, memory, IO, analog, RF and sensors
- 3D Memory & Logic for High Performance Computing, Mobile Computing, and AI acceleration
- Application, product, or test chip case studies
- 3D design methods and EDA tools
- Chip-package co-design for 3D
- Signal and power integrity, and ESD in 3D
- Thermo(-mechanical) analysis and -aware design
- Fault Tolerance, Reliability, Safety, Security techniques for 3D architectures
- Test, KGD/KGW methods, DFT, debug/FA for 3D
- Economic benefit/cost trade-off studies
- Standardization initiatives
Submissions are invited in the form of (extended) abstracts not exceeding two pages and must be submitted by email to:
All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions will be accepted for oral presentation or poster.
At the workshop, an Electronic Workshop Digest including Slides & Posters will be made available to all workshop participants.
Paper Submission deadline January 22, 2023 Extended 17 feb 2023
Notification of Acceptance February 5, 2023 Extended 24 feb 2023
Presentations and posters ready March 26, 2023
Workshop Wednesday 19 April 2023, 14:00PM – 18:00PM
- General co-Chairs
- P. Vivet – CEA-LIST (FR)
- M. Badaroglu, Qualcomm, (BE)
- Program Chair
- P. Ramm, Fraunhofer EMFT (GE)
- Special Session Chair
- S. Mitra, Stanford University (USA)
- Industrial Liaison Chair
- Eric Ollier, CEA-LETI (FR)