After a one-year hiatus, 3DIC will once again unite 2.5D/3D researchers and developers from all around the world. This year’s conference employs a hybrid format of in-person events and virtual events. Talks, panels, exhibits, papers, and discussions will foster a stimulating exchange of ideas and technical information.
So much has changed since the first 3DIC conference in 2010! 3D integrated circuits have moved from academic curiosity to solid commercial reality. The underlying technologies continually improve and evolve, incorporating new methods and resources. Today’s hot topics include chiplets, photonic interconnect, micro-die handling, and exotic substrates. This conference will focus on the research and science of 3DICs. It will cover relevant 2.5D/3D topics from manufacturing, processes, materials, and equipment to circuit designs, design methodology, and applications.
Please register at the conference website: www.3dic-conf.org.
Highlights of this year’s conference include the following:
- Presentations from major companies including AMD (Raja Swaminathan), Intel (Debendra Das Sharma), Qualcomm, and TSMC (Doug Yu)
- Presentations from companies developing new 3DIC technologies including Cadence (John Park), GINTI, (Mitsumasa Koyanagi), X-Celeprint (Bob Conner), Xdisplay (Chris Bower) and Xperi (Gil Fountain)
- Presentations from academic and research institute thought leaders including Mitsumasa Koyanagi (Tohoku), Tanay Karnik (Intel), Mark Rodwell (UCSB), Pascal Vivet (CEA-LETI), Madhavan Swaminathan (Georgia Tech), Tetsu Tanaka (Tohoku), and Sung Kyu Lim (Georgia Tech)
- Tutorials on stress management in 3DIC (Ephraim Suhir), and technology and design (Paul Franzon)
- Panel session entitled “Challenges for 3D IC and Chiplets” organized by Jan Vardaman
Call for Papers
Abstracts for papers are solicited on all 3D IC topics including, but not limited to, the following:
Technology: Materials, equipment, wafer handling, diverse substrates, Through Silicon Vias (TSV), alignment, bonding (thermo-compression, electrostatic, hybrid, temporary adhesive), de-bonding, wafer cleaning, thinning, dicing, chiplets, interposers (active, passive), 3D integration (monolithic, heterogeneous), capacitive coupling, inductive coupling, multilevel epitaxial growth, etc.
Design and CAD: Synthesis, design flows, signal design, power integrity, thermal considerations, mechanical stress, reliability, test, techniques, analysis, etc. Applications to be considered may include imaging, memory, processors, communications, networking, wireless, biomedical, sensors, SOC, MEMS, DSP, FPGA, RF, microwave, millimeter wave, analog circuits, biomedical circuits, photonics, optoelectronics, etc.
- Abstracts should be about 500 words in length
- Some figures and tables can be included
- The deadline for submissions is July 31
- Notifications will occur by August 31
- Full papers in IEEE format will be required by September 30