Now in its 11th year, 3D Architectures for Semiconductor Integration and Packing (3D ASIP) is firmly established as the leading industry event in 3D integration and packaging. This conference presents a broad, yet thorough perspective on the techno-market opportunities and challenges offered by building devices and systems in the vertical dimension, and provides participants the unique opportunity to gain the latest technology and market insights on 3D integration and packaging efforts, and technology and industry trends impacting this dynamic arena.
This 3-day event kicks off with a full day Pre Conference Symposium followed by a 2-day Conference.
Pre-Conference Symposium Session 1: 2.5/3D-IC Design Tools and Flows
Wednesday, December 10, 2014 8:30 a.m. – 12:30 p.m.
Herb Reiter, President, eda2asic Consulting
Within the last several years many IC design teams developed, in cooperation with their supply chain partners, about 100 evaluation units, to define design flows and better understand the benefits of stacking dice on interposers or vertically. Likewise the manufacturers used these evaluation units to hone their manufacturing flows and drive cost-reductions. Now both sides are ready to develop designs for volume production and need EDA tools to walk the fine line between costly over-design and unreliable under-design.
In this session EDA vendors and IC manufacturers outline their cooperation to provide system and IC designers the means to implement and verify their ideas in 2.5/3D-ICs.
Session 2: 3D Integration: 3D Process Technology
Wednesday, December10, 2014 1:30 p.m. – 5:00 p.m.
Phil Garrou, Microelectronic Consultants of NC
With the 2014 announcements of TSV-based memory stacks from Micron, Hynix, and Samsung the Era of 3D-IC has officially begun. RTI International’s 3D ASIP pre-conference symposium will take a quick look at the current status of the 3D marketplace and then a more detailed look at the status of 3D TSV-based processing technology.
3D ASIP Conference Thursday-Friday, December 11 & 12, 2014
A Design Ecosystem for Internet of Things, How 3D IC Standards will Enable a New Growth Paradigm
President and CEOSi2, Silicon Integration Initiative
2.5D and 3D Memory Solutions: An Overview and Outlook
Director, Hybrid Memory Cube Solutions, Micron Technology
An UltraScale 3D FPGA
VP Silicon Technology, Xilinx
Following the keynote session, the remaining sessions will cover the following topics:
- Memory and More than Moore
- Perspectives on Manufacturing and Costs
- Design Analysis and Modeling – Signal Integrity, Thermal and Power Considerations
- The World in 2.5D – Interposers
- Monolithic 3D Integation – An Emerging Reality?
- 2.5/3D Systems – Bringing it all Together
- Featured PANEL SESSION: How can we further strengthen the foundation for 2.5/3D-IC Pathfinding?
For more details on the agenda, networking, and registration, visit the 3D ASIP Website.