06/08/2015 -10:30 am - 12:00 pm

Location: Moscone Center

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52DAC_logoStacked  DRAM in 3D configuration requires through silicon via (TSV) technology. First-generation integration of logic an memory devices typically uses silicon interposers. Successful integration of these devices with logic dies on interposer, package and board requires innovative low power logic design techniques, co-design methodology, advanced EDA tools, manufacturing requirement and supply chain infrastructure. Due to thermal requirement, low power logic design plays a critical role in producing a cost effective and reliable 2.5D/3D system.

This session provides the fundamental knowledge, individual skill sets and the most recent state of the art technologies used for 2.5D/3D integration. In particular we present low cost silicon interposer, low power logic design techniques and EDA tools and methodologies to perform system co-design.


  • Farhang Yazdani – BroadPak Corp., San Jose, CA
  • John Park – Mentor Graphics Corp., Longmont, CO
  • Rajiv V. Joshi – IBM T.J. Watson Research Center, Yorktown Heights, NY

For more DAC 2015 events, visit the DAC website.