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Send us a text In this episode, Francoise speaks with Simon McElrea, an interconnectologist, about his career in and the evolution of interconnectology, emphasizing its importance in semiconductor packaging. McElrea discusses his roles at semiconductor start-ups like Vertical Circuits and Invensas; his foray into wireless charging at Energous and FreePower; and his return to the […]
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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible? The post What Comes After HBM For Chiplets appeared first on Semiconductor Engineering.
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TSMC’s Fab 21 in Arizona already produces A16 processors on the N4P node.
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Send us a text In this episode, Françoise von Trapp talks with Onto Innovation’s Monita Pau and Jiangtao Hu about metrology for advanced packaging – why do we need it? What are the challenges, and how do we solve them? In semiconductor manufacturing front-end processes, metrology has always been a critical step to ensure consistency […]
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Intel’s CHIPS Act funds are reportedly being delayed as Washington requests a more concrete manufacturing roadmap from the company.
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TECHCET has identified a potential strain on US semiconductor manufacturing capability as Chinese export restrictions on key materials have been announced. Material Export Restrictions Poised to Strain Semiconductors was posted by Shannon Davis on Semiconductor Digest.
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Send us a text In this episode, Tarak Railkar and Benson Chan join Françoise von Trapp for a preview of The IMAPS International Symposium 2024, which takes place in Boston from September 30 to October 3, 2024. This year’s symposium focuses on heterogeneous integration for paradigm-shifting microelectronics and photonics. It will feature a five-track technical […]
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The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More The post […]
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Send us a text In this episode, Françoise von Trapp speaks with Bruce Kim, of SurplusGLOBAL, for an update on the semiconductor secondary equipment market, and how the US. and European Chips Acts are impacting it. They also discuss the trend of top-tier OEMS prioritizing the development of innovative technology rather than investing in legacy […]
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This new superconductor could potentially reduce errors in quantum computers. https://www.tomshardware.com/tech-industry/quantum-computing/uc-riverside-team-develops-new-superconductor-material-for-quantum-computing
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A UCIe case study. The post Intel and Cadence Collaboration on UCIe: Demonstration of Simulation Interoperability appeared first on Semiconductor Engineering.
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Send us a Text Message. In this episode, Françoise von Trapp and underfill materials expert, Dick Jensen, NAMICS corporation explore the societal and technological challenges that impact microelectronic materials development. The conversation focuses on the evolution of underfill materials development over the past 30 years. They discuss the importance of underfill materials in semiconductor manufacturing, […]
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The chip industry can’t just continue to scale by focusing on transistor poly pitch or gate oxide thickness. The post Intel 18A Advanced Packaging is Key to Tech Leadership appeared first on EE Times.
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Send us a Text Message. This episode was recorded live at SEMICON West 2024 – SEMI’s flagship tradeshow where the global industry gathers to showcase its latest products and technologies; and discuss topics critical to the industry’s growth. Two of these continue to be Sustainability and Workforce Development. Today’s guests will address both these topics. […]
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U.S. government to support TI’s fab projects in Texas and Utah with $1.6 billion in direct funding and up to $8 billion in investment tax credits.
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The demand for high-performance and sustainable computing and networking silicon for AI has undoubtedly increased R&D dollars and the pace of innovation in semiconductor technology. With Moore’s Law slowing down at the chip level, there is a desire to pack as many chiplets as possible inside ASIC packages and get … Read More The post […]
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Send us a Text Message. The semiconductor industry supply chain continues to capture attention as general awareness about the importance of semiconductors in our everyday lives grows. The news of global expansion and ongoing delays of new fabs coming online is constant. But have you ever stopped to think how complicated it is to outfit […]
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As TSMC fights to bring its new Arizona fabs online, the company learns the Taiwanese way isn’t going to work in America and needs to change.
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The semiconductor industry has integrated ever more functionality into smaller footprints and is starting to build upward. With the rise of three-dimensional integrated circuits (3D ICs), designers can pack more processing power and functionality into smaller spaces. However, this new dimension brings with it a host of challenges, including mechanical stresses and thermal effects, that […]
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Recent developments address imminent needs of advanced nodes and packages, but not all the pieces are in place yet. The post Metrology And Inspection For The Chiplet Era appeared first on Semiconductor Engineering.
