Foveros packaging technology uses 3D stacking to enable logic-on-logic integration. This provides tremendous flexibility for designers to mix and match technology IP blocks with various memory and I/O elements in new device form factors. Products can be broken into smaller chiplets or tiles where I/O, SRAM, and power delivery circuits are fabricated in a base die and high-performance logic chiplets or tiles are stacked on top. When combined with Intel's embedded multi-die interconnect bridge (EMIB) it allows for the interconnection of different chiplets and tiles with essentially the performance of a single chip.